Jay Dass Email & Phone Number

Folsom, Ca, Us

Folsom, Ca, Us

Roseville, California, Us

Supporting existing and developing new HMI/SCADA/MES solutions across various manufacturing industries that meet customer specifications and functional requirements.

San Jose, California, Us

Managed the product development of the newest NVMe SSD storage for data centers. I lead cross-functional teams from the firmware, hardware, software, validation, reliability, operations, and marketing departments to plan, coordinate, and deliver high-quality products on time. I keep the lines of communication open between the executive team and all levels of management to discuss project concerns and progress, including choices that have an influence on products and programs. Meetings with executive staff for PLC milestone reviews and deep dive reviews are led and facilitated by me.

Santa Clara, California, Us

During this time, I oversaw a team of five engineers who were responsible for pre-silicon validation. We validated clock circuit IPs on SoC and PCH for both functional and mixed-signal testing, including clock units, LDO, and general-purpose I/O. I created validation strategies for PCH and SoC testing using digital simulation. I created validation methodologies, directed task priorities for the current project, and looked at future project resources and head counts. Together with circuit IP architects and micro-architects, I analyzed recently suggested features and IP architecture.• Effectively planned and coordinated validation activities for two offsite contractor groups and 10 engineers based in India to reduce local headcount costs

Santa Clara, California, Us

During this time, I created and implemented front-end pre-silicon validation procedures for Intel's intellectual property related to clocks and circuits. I worked as an engineer for Intel's clock circuitry IP, which is used in SOC and chip set products, as a senior pre-silicon validation engineer. I worked closely with senior design engineers to analyze new features and plan their implementation. For new features of young engineers, I made test plans. I served as a team mentor and project manager for the application of optimal QA procedures. I oversaw the company's use of IP to execute numerous projects simultaneously, managed resources, and made sure testing of important features was completed on time.• Cut time for new validation development by ~50% through execution of validation framework re-use methodology• Designed and deployed new chip design configuration testing framework to increase code coverage from 20% to 100%• Developed new emulation strategy to cut the amount of coding required for new emulation models by 50% by making models reusable for new chip design projects with slight adjustments.

Santa Clara, California, Us

During this time, I held the position of Agile Product Owner for processes and quality control for one of the company's manufacturing validation software solutions. I used best QA practices to organize sprints and analyze the team's QA operations on a two-week cadence. On roadmaps, targets, test plans, and problem-solving strategies, I cooperated with the product owner and software developer. I worked as a QA architect and created a range of automated software QA technologies to speed up validation and problem finding.• Defined and established standardized filing process for reduction in time needed to complete bug fixes from four to two working days• Led, trained, and empowered 10 people on effective ways of product, coding standards, and testing procedures• Reduced testing time by approximately 75%, increased release times, and maximized revenue through effective design and development of standard automation testing tool• Redeemed 20 hours of engineering resource per day by designing a tool with continuous integration capability, usable UI interface, test content, and validation library• Accelerated on-time PPV (internal manufacturing validation process consisting of a 'processor and platform') software releases from 60% to 90% by implementing new validation strategy processes.• Developed test regression matrix to lower time required to create new collateral for each new product from one month to 1.5 weeks, while increasing overall volume of projects from one to 15

Santa Clara, California, Us

During this time, I developed and maintained SOLID C# code for circuit analysis testing tools, enabling the use of chip probes for debugging and general IO controllers, thermal controllers, and other circuit analysis supporting hardware. Thanks to my successful coding and design, Intel's first mobile cellular/mobile chip project was made possible.• Directed and influenced four engineers in cellular and mobile chip code design• Saved three resources in tool development by leading planning and implementation of software for new standard in-house thermal controller for circuit analysis

Santa Clara, California, Us

Additional Experience as a Pre-Silicon Validation Expert & Technical Lead & Senior Component Design Engineer at Intel Corporation, Folsom, CA.