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Understood the functionality of Synchronous and Asynchronous FIFO by designing RTL in Verilog. Developed a test bench and multiple test cases for verification of FIFO behaviour.Setup UVM TB Setup for asynchronous FIFO design with two master interfaces for understanding o7 UVM constructs.HDLHVLVerification : Verilog : System VerilogDevelop both agents with components such as sequencer, driver, monitor, interface, coverage, score board.Created SV test bench components… Show more Understood the functionality of Synchronous and Asynchronous FIFO by designing RTL in Verilog. Developed a test bench and multiple test cases for verification of FIFO behaviour.Setup UVM TB Setup for asynchronous FIFO design with two master interfaces for understanding o7 UVM constructs.HDLHVLVerification : Verilog : System VerilogDevelop both agents with components such as sequencer, driver, monitor, interface, coverage, score board.Created SV test bench components generator, BFM, interface, monitor, coverage, scoreboard that improved reusability of test bench.Made TB more reusable by using the concept of a virtual sequencer and virtual sequences test case coding. Show less

Developed the RTL design of configurable memory and test bench in Verilog with multiple test cases by understanding memory and using Verilog.Construct such as parameter, front door-backdoor access task, loops etc.Debug functional test case memory write/read by analysing waveform.

AXI 3.0 is an AMBA protocol used for high performance applications.Developed and integrated master and slave UVC for AXI along with components such as sequencer, driver, responder, monitor, coverage & scoreboard under it.Understood features of AXI such as fixed, incremental, wrap and narrow transfers by creating test library and sequence library for such test cases.Debug functional test cases by analysing waveform.

Developed and integrated master and slave UVC for AXI along with components such as sequencer, driver, responder, monitor, coverage & scoreboard under it.Understood features of AXI such as fixed, incremental, wrap and narrow transfers by creating test library and sequence library for such test cases.Debug functional test cases by analysing waveform.

Understood the functioning of the SPI controller and designed RTL in Verilog using FSM.The design had two interface, one APB use for configuring internal SPI registers and other the SPI interface use for serial communication with slaves.In test bench, different test case are generated by configuring SPI registers of SPI for write and read operation and number of transactions to slave. Scanned with OKEN Scanner

Understood interrupts and the functioning of Interrupt Controller by implementing RTL in Verilog. The design had two interfaces: one that APB use to programme priority register in controller and another that the Interrupt Controller used to get peripherals serviced by the master on a priority basis.Develop different test cases for various interrupt handling possibilities.Develop the Interrupt controller architecture with processor and peripheral interfacing.Other skills : Digital… Show more Understood interrupts and the functioning of Interrupt Controller by implementing RTL in Verilog. The design had two interfaces: one that APB use to programme priority register in controller and another that the Interrupt Controller used to get peripherals serviced by the master on a priority basis.Develop different test cases for various interrupt handling possibilities.Develop the Interrupt controller architecture with processor and peripheral interfacing.Other skills : Digital Design Show less

B.Tech, Ece

Intermediate

Ssc