Jayant Gautam Email & Phone Number

Noida, Up, In

Worked on Analog Design Environment (ADE),Spectre APS, Spectre X netlists , circuit simulation and mixed signal simulation tools AMS designer, Incisive/Xcelium, Simulation Environment Simvision, Viva ,Statistical analysis Monte Carlo/Corner, Reliability/aging analysis , SPICE/Spectre formats analog/digital design ,Spectre/ SpectreRF analysis – TRAN,DC,AC,PSS, PNOISE

Noida Area, India

Worked on Cadence Design Framework (DFII), schematic capture (VSE), Analog Design Environment (ADE) , Analog/Mixed-Signal IC custom layout design, PCELLs , CDFs and Skill Programming LanguageSupport for cadence custom flows, tool development ,installation, Virtuoso Constraints, Modgen

Banglore

Worked on Core Memory for Global Foundry 14nm using finfet technology.ARXSXXXBNK2KBLP Custom Memory• Worked on 16nm Finfet SRAM(ARXSXXXBNK2KBLP) Memory for AMD India Pvt. Ltd .• Development of Control block & RoutT and RoutB cells with all verifications.• Development & Routing of Slphdr cells with its all verifications.• ECO & Electromigration fixing(EM)

Banglore

1). TSMC 16nm (finfet) ram_llsp122, ram_llsp111Instance level DRC,LVS,ERC, Cell Checker2) . Samsung 14nm finfet ram_sllsp122 Made block ROWDEC from scratch for both compilers ram_sllsp111, ram_sllsp111Done verification for both & control block , Instance level Verifications.3). Generate Lef for custom memories for 14nm & made phase detector for rise & fall and have done all Verifications.4) Worked on 14nm LLPDP Layout editing done for several blocks of Control and IO… Show more 1). TSMC 16nm (finfet) ram_llsp122, ram_llsp111Instance level DRC,LVS,ERC, Cell Checker2) . Samsung 14nm finfet ram_sllsp122 Made block ROWDEC from scratch for both compilers ram_sllsp111, ram_sllsp111Done verification for both & control block , Instance level Verifications.3). Generate Lef for custom memories for 14nm & made phase detector for rise & fall and have done all Verifications.4) Worked on 14nm LLPDP Layout editing done for several blocks of Control and IO Complete LVS/DRC/ERC/Antenna checks/boundry checks verification of physical blocks. Show less

SYNOPSYS Suite: Galaxy Custom; ,ICV, Hercules 28 nm One port register file Memory Compiler Design 28 nm High Density Two port register file Memory Compiler Design Leafcell Layout Verification Leafcell/Instance level DRC; 28nm High speed one port register file Memory Compiler DesignMiniarray Delievery Leaf cell development,Placement & Routing of Bist I/O cell with DRC,LVS Leafcell DRC/LVS, Instance level DRC, ERC check, chcells extraction and full QA

JOINED Internship Program At DKOP LABS PVT. LTD, During Internship worked in following areas:1). VERILOG, SHELL SCRIPTING2). DIGITAL DESIGN3). DONE PROJECT IN 10GB ETHERNET RECEIVER USING VERILOG4).TCL/TK AND DONE PROJECT EIGHT QUEEN SOLVER

M.Tech, Vlsi

Activities and Societies: CHIP FABRICATION LAB, Dept of electronics NMU

Master Of Technology; M.Tech

Class: 1st class

Bachelor Of Technology (B.Tech), Electronics And Communication