Jaymin Patel Email & Phone Number

- Hands on with different domain of Front end design covering Requirement capture, functional specification doc, Design specification doc, Micro-Architecture definition, RTL design with verilog and VHDL for ASIC and FPGA, Module level functional verification and gate level simulation, FPGA Synthesis, Timing closure and board level validation- Worked on cutting edge memory IP design such as Universal Flash Storage (UFS) Host Controller - Worked on industry standard protocols such as DDR2/3, I2C, SPI, I2S, EMIF, ITU-R BT-656/1120- Exposure to FPGA validation of video processing algorithms with Xilinx ChipScope analyzer and Oscilloscope- Worked on entire FPGA design flow including RTL coding/Integration, Verification, Synthesis, Timing closure and board validation- Developed test-bench and video processing algorithms behavioral models in verilog for module level verification

Listed skills include Systemverilog, Asic, Soc, Verilog, and 1 others.