Jay Sarkar Email & Phone Number

California, United States

Boise, Idaho, Us

Lead with establishing data science methodologies, pathfinding, research and modeling bearing strong fidelity to design and architecture of memory/storage systems, while leveraging hardware-software co-design principles and co-optimization. My focus tends to span ML-based adaptive policy designs for system architectures relevant to emerging/current cloud, datacenter memory and storage technologies, and associated information processing.

Boise, Idaho, Us

Technical leadership at enabling formation and growth of a new systems Data Science team at the intersection of silicon technology, systems and circuits.

San Jose, Ca, Us

Focused on pathfinding and methodology developments for predictive & inferential machine learning driven advanced technologies and architectures. Led with pathfinding research and guidance on datacenter solid-state storage, resulting in original innovations on prognostics and software-defined/disaggregated/composable storage systems, and robust design for fail-in-place and in-field reconfigurability. Specific technical areas included conceptualizing and developing interpretable, reproducible embedded-ML models for policy design coherent with causality (thus, fundamentally generalizing to advanced designs) from high-dimensional behavioral data of SSD-internal workload interactions - by anchoring, leveraging and reasoning within the framework of system design, architecture and physics. Also published/established peer-reviewed, first known comprehensive, quantified population reliability modeling framework fundamental to SSD technology, with respect to experienced workloads and I/O data throughput.

San Jose, Ca, Us

Led with technical ownership for R&D, and implementation of knowledge-based statistical reliability validation framework for robust design, and establishing statistical/predictive design/physics-aligned methodologies/models of solid-state storage system reliability - working across a corporate joint-venture and acquisitions. Also led initiation of a predictive analytics framework for solid-state storage, along with design and deployment of a telemetry solution for external and internal stakeholders, towards a data product and fleet health management.

San Diego, Ca, Us

In an acquired start-up division, owned multiple, diverse areas of R&D on a novel microelectromechanical system-based low-power display technology. Established ab-initio characterization methodologies, with data-driven models for figures-of-merit demonstrating multiple design improvement avenues by factors of 2x – 10x.

Santa Clara, California, Us

Researched and developed Phase Change Memory (PCM, 3D Xpoint) technology, to enable novel low-latency persistent memory architectures at Intel and Numonyx (Intel spin-off, now Micron). Responsibilities included developing the core physical, statistical and electrical models of operational evolution and reliability of array/device, incorporated in state-machine microcode-algorithm and silicon technology co-designs. Contributions played key role in enabling the technology to exceed Flash endurance by 10x to 1 Million cycles, with subsequent volume commercialization at Numonyx and Intel.

Santa Clara, California, Us

Fundamental and applied research on Phase Change Memory Technology, as part of doctoral dissertation research aligned with Intel's technology road-map.

Phd, Electrical & Computer Engineering

M.S., Applied Physics

Bs, Physics