Providing leadership in managing a high performing engineering team to success across multiple physical design domains.

Technical leader, responsible for all areas of backend design convergence and execution from synthesis to GDS on many complex multi-domain partitions. Owned backend project execution across multiple Geo’s, driving improvements across multiple vectors to pull in and deliver an aggressive schedule.

Individual technical contributor responsible for delivering bottoms-up elements of chip design including but not limited to block-level custom layouts, FUB-level floor plans, abstract view generation, RC extraction and schematic-to-layout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, auto-place and route algorithms, floor planning, full-chip assembly, and verification.