Cellular Products/Networking/ Multi-core Products•Designed experiments and summarized results for matrix CZ lots (including Vmin/Vmax/Fmax and AC timing analysis across temperature/splits/voltages)•Improved yield/reliability by working with cross functional teams to implement a better design allowing testing at guardbands, improving margins by an average of 77mV across 71 tests, decreased functional fallout from 34% to 0.07%, and dropped ELFR failures from 5.2% to 0%. •Generated and implemented Burn-in code for Scan/Memory testing used in qualification.•Spearheaded GRR and NBTI processes and documents for Cellular group; created NBTI qual and shmoo flows •Debugged the following issues using the EVB and brassboard: correlated DSM to ATE readings with different active well bias settings, esdhc verification, memory read margin analysis.•Released additional emulation tools during an Emulation rotation (Oct 2006-Feb 2007)•Completed the 1st hardware/emulator interface verification: ESDHC/CPLD LED's•Power/Speed Modeling and binning predictions•Test time reduction (cost improvements), yield improvements, and cycle time reductionstaught SPC, JMP, Data analysis classes, certified FSL Six Sixma Instructor

•Co-led SPC renewel in the factory; starting with a new monitoring method, culture change, and training. Estimated annual savings of $264k.•Led a weekly cross functional SPC team to review factory issues flagged by the new SPC system; set up Cpk reporting/goals and drove actions to improve SPC metrics•Championed the FMEA process to prevent scrap, decrease cycle time, and improve yield. Reduced the overdue FMEA's from 45% to 0% in 6 months.

•Introduced, characterized, and successfully qualified many new parts on multiple technologies.•Supported successful technology transfers: UDR TSC8/ SmartMos7 SMIC/SmartMos8 •Designed, analyzed, and reported on experiments/trends to optimize processes, meet target yields, and reduce cycle time/cost•Analyzed parametric trends/correlations to ensure ongoing process control of electrical targets and inline parameters-SPC•Increased yield on SM7 high runner by 20% through reducing cleans contamination and process modifications•Analysis of root cause and implementing fixes to reduce scrap •Led the GOI/Charging Team to reduce scrap. The team successfully completed all goals by implementing hardware/process changes. QBD-charging scrap dropped from 4.83% to 0%. Changes saved $43k/week.•Responsible for the PROMIS KeyUser team which controls the inventory processing steps. Led the successful conversion to the CBL baseline. Verified other engineers changes before implementation.•Drove the frontend yield team to meet its goal of 4% yield improvement on RFBiCMOS processes and 2% on SM7.•Led a classprobe reduction team to reduce parametric test time for capacity needs without reducing quality