Jeff Ding Email & Phone Number

- Bring-up FPGA/Veloce and released boot ROM for the 4TB 3D NAND SATA SSD controller.- Managed the overall operational activities for the Host firmware team for the WCS NVMe PCIe project.- Helped releasing WCS sample to Microsoft.- Accomplished tasks for VU commands, evaluation board support and chip bring-up.- Implemented and delivered operational and non-operational power states.- Designed core dump process and utilities as part of fatal error handling.- Proposed a firmware update roll-back mechanism and coordinated development among NAND boot loader, host boot code and FW manager.- Worked with HW designer on Thermal/Power throttling, including verifying design change and finding possible FW workaround.- Supported Power-loss/PLP/Super CAP health monitoring, including FW implementation, prototyping, and debugging. - Implemented a NAND flash exerciser/BIST FW, including NAND cell vth distribution for SLC/MLC NAND programming failure analysis.- Prototyped NVMe management interface/BMC through the slave SMBus/I2C.

- Helped SDK firmware release for PMC 12G SAS SSD.- Designed power state machine/timers for PMC 12G SAS SSD based on T10 power condition specification.- Completed fatal core dump implementation.- Designed reliable persistent data mechanism with reduced flash erase.- Designed PCI VPD storage access for PMC 12G SPCv SAS/SATA HBA including VPE TC PCI PF service/cache pool/flash journaling with reduced flash erase.- Resolved PMC 12G SAS HBA multi-threading and cache coherency issues.

-Constructed SSP/STP/SMP/XOR core module for Marvell 6G SAS/SATA RAID HBA's firmware/driver.-Provided firmware and Windows driver and worked with ASIC team on FPGA verification and chip bring-up for 6G SAS/SATA controller.-Added SAS SES support including virtual device over I2C and SGPIO for 6G SAS/SATA RAID HBA.-Prototyped a SAS/STP/SMP async discover engine for 6G SAS HBA.-Designed a five-phase SAS Error Handling and multi-path for SAS HBA.-Added support for T10 data protection (PI), Type 0/1/2/3, and extended SCSI commands.-Initiated SAS2 zoning and SMP target firmware functions for Marvell 36 port 6G SAS/STP expander.-Prototyped eMMC core/flash DMA/ECC/ONFI controller firmware for SD 2.1/eMMC 4.4.1 slave flash controller.-Added write-buffer and read-cache and FTL logical block mapping for eMMC flash controller. -Worked with ASIC team on eMMC 4.4 boot and alternative boot operations.-Supported all eMMC commands and eMMC LDPC, Interrupt mode, WP, Lock/unlock, BKOPs, Sleep/Wake features.

-Maintained non-raid/host-raid linux open source driver for Adaptec SAS/SATA razor controller. -Coded SAS/SATA CSMI utilities for SSP/STP/SMP verification and error recovery testing. -Designed a W2K fail-over/load-balancing filter driver for fibre channel controllers. -Provided Windows API DLLs for Adaptec's RAID controller. -Maintained Windows/DOS ASPI, Win95/NT4 SCSI miniport drivers for ISA/PCI SCSI host adapters. -Provided host adapter detection engines for Adaptec EZ-SCSI software. -Ported ucd-snmp SNMP server to embedded HardHat Linux firmware with uClibc. -Completed SNMP extension agents for iSCSI/Fibre-Channel network storage controllers under Windows and RedHat LINUX(ucd-snmp AgentX). -Initiated SNIA iSCSI IMA 1.0 plugin and library coding for Windows and Linux as a sourceforge developer. -Developed RPC, Client/Server, remote-management programs for FC controllers with Windows SSPI authentication and MAPI email notification. -Researched into and prototyped the thin TCPIP/Ethernet/SCSI Sever(ASPI over TCP/IP). -Prototyped first generation Windows TDI filter driver for GigaNIC TCP offload. -Prototyped Web-based configuration utility in HTML/Java script for iSCSI controllers. -Provided Linux GTK+/GDK(Glade) utilities for iSCSI controllers.