Consulting and contracting with various clients around the world:Verification of new CHI (ARM's Coherent Hub Interface) subordinate block attached to an existing memory controller. Verification lead for proprietary, high-speed, low-latency serial protocol IP. Wrote the verification plan and managed the schedule to hit client's milestones for two separate SOCs using the IP. Managed verification engineers from Verilab and the client to complete verification on time.Verification of audio processing DSP block. Worked with a team doing mixed signal & DSP UVM verification of an audio processing IP block. Performed requirements tracing back to product requirements document.Verification of FPGA based video processing block. Integrated a C reference model into a UVM/SV testbench, used UVM to generate frame data and checked that DUT response matches C prediction.Verification lead for a high speed, low latency networking system. The team designed and verified two FPGAs (NIC & SWITCH) for a proprietary networking protocol. Planned, architected and implemented UVM-like testbenches for both components. Lead team of three verification engineers working on both projects. Assisted software team with application and laboratory debug of the FPGAs.Verification team member working on verification of DDR based system using UVM/SystemVerilog testbench. Responsible for register verification using uvm_reg. Wrote scripts to generate UVM code from JSON register descriptions provided by client. Developed testbench infrastructure to verify reset and boot sequence.

When I joined the team, there was no verification flow to speak of. I worked with the analog and digital engineers and the CAD team in order to design and implement a mixed signal verification methodology. We used the existing Cadence toolset and licenses to put together an analog-top, UVM/SV + Verilog AMS based verification environment. I helped the analog designers implement Verilog-AMS based real number models (wreal) of their blocks that were used in the top level simulations.I implemented a full regression system that made use of Jenkins and Perforce to run simulations on the latest schematics and RTL nightly. Implemented a continuous integration (CI) flow using Jenkins and Perforce. I also wrote a Jenkins plugin based on xUnit that would report pass and fail status per simulation for nightly regressions.I was responsible for the top level and all digital verification of power manager product line with voltage, current, and temperature monitoring and digital and high voltage control IO. Power manager is low power, low cost, high voltage (~12v) part.

When I arrived at Synopsys the team was using a unique home-grown mixed signal verification flow based on a PLI real number modeling library (see "Sending Analog Values Along Digital Wires" below). While there I worked with the analog and digital teams to codify a set of rules and guidelines for analog designers and analog modelers that enable mixed signal simulations.I also worked with a few of the analog engineers to set up a cosimulation flow that paired SystemVerilog with FastSPICE that allowed us to run full chip mixed signal simulations (see "Mixed Signal Cosimulation Methodology" below).Verification of high speed serial mixed signal IP: PCI Express, SATA, XAUI, and USB 3.0.Verification Lead * Five major chips verified, all functional in first silicon. * Architect VMM based System Verilog verification environment. Coverage driven, constrained random verification. * Coordinated work of several engineers on various continents Responsible for complete verification of digital portion of IP and testchip * Verification planning and scheduling * Testbench and test case development * Functional and code coverage * Assertions (SVA), * Regression testing and debuggingMixed Signal Verification: * Cosimulated (Verilog + FastSPICE) analog and digital blocks to verify analog behavioral models. * Present papers on cosimulation methodology and mixed-signal additions to Verilog using PLI.Scripting: * Develop MySQL based web interface to regression testing results * Develop simulation run and regression scripting for Sun Grid Engine distributed computing in Perl

Product Manager for PCI Express Verification IP (VIP)* Developed VIP based test suite* Wrote VIP code in TestWizard* Pre-sales and post sales customer support* Maintain databookSimCluster Applications Support* Install Avery's SimCluster (parallel Verilog environment) at several customer sites.* Work with R&D to add and test features

Verification Engineer - Gigabit Ethernet Switching productsLead architect for Ethernet switch verification environment:* Reusable and portable, used on five different chips* Coverage driven, constrained random environment with assertions, written in Specman E* Supported various networking protocols, IEEE 802.3, 802.1q, MPLS, VLAN Tagging* Various IO connections: XAUI, GMII, PCIDeveloped various training materials for engineers new to the environment and Specman, including presentations, training classes, and written documentation.

Responsible for a RTL development of a major section of design of an Ethernet switch, testing debugging and adding featuresDesigned and implemented an object oriented verification component library in VERA for reusable verification of networking components, including Ethernet packets and various *MII interfacesWrote test plan for silicon evaluation in the lab using IXIA Traffic Generators and TCL scripting to validate silicon