Responsible for development of proprietary interface models to accelerate simulation. Duties included tracking and fixing bugs in models, updating of interconnect files in SOC design hierarchy utilizing Connit, and being responsible for diagnosing and fixing failures from regression runs.

Designed and maintained SOC block-verification testbenches utilizing Specman E and System Verilog/UVM (SV/UVM) with constrained random methodology for six generations of BME module in HDC SOCs. Implemented and attained 100% functional coverage and 100% code coverage. RDL and Blugen were used to generate register models for use in the testbenches. Also worked on testbenches for Servo and SATA interfaces. Debugged issues within testbench and/or DUT. Debugged and fixed a challenging problem with DDR model that caused intermittent false failures.Developed configurable and reusable buffer memory model using SV/UVM. Designed APB-protocol checker using Verilog assertions. Created testbench architecture/testplan documents. Initiated bug-tracking reports for issues found by testbench to be fixed and verified in current version or in subsequent revision of SOC.

Simulated and fixed known issues in first generation of Merlin Fibre Channel (FC) core for next version Raid Storage Processor(RSP) ASIC. Simulated disk microcontroller with Merlin core contained in RSP to verify FC protocol operation as an initiator.Created system simulations to test firmware read/miss and write-through flows of RSP using disk model and host model created to verify function and assess IO performance. Verified latest generation of RSP including disk microcontroller and SAS/SATA core using FPGA emulation platform with firmware and drives.Performed signal integrity analysis of 4-Gigabit FC link between RAID controllers on IBM Bladecenter using Le Croy and Tektronix Serial Data Analyzer. Designed and maintained production firmware for redundant controller using disk microcontroller and Merlin FC core to perform cache mirroring and enable symmetric LUN flows for bound controller operation. Maintained disk controller firmware for SAS/SATA protocols. Diagnosed and fixed firmware issues involving cache, host, and disk functionality using firmware trace logs and state captures of RSP. Performed analysis of IO performance using Iometer and Finisar. Tested and debugged concurrent firmware upgrade of bound controllers on Bladecenter. Created production firmware builds for use with RSP on Bladecenter and Mac Pro and Xserve using CVS and in-house process.

Designed data buffer for 100Mhz PCI-X interface to implement write-buffering and split-completion read operations. Designed data buffer for 66Mhz PCI interface to implement write-buffering and read-buffering with read ahead.Designed and verified two different versions of XOR ASICs for RAID controller using Viewlogic schematic capture and simulation tools. Installed design tools for RAID controller design team. Designed portions of DMA chip. Used Synopsys Design Compiler and Toshiba design tools to perform timing analysis on RAID chip set consisting of XOR, DRAM (fast page mode) memory controller, CPU interface, and DMA chips. Modified firmware to test bus arbiter in XOR ASIC. Responsible for XOR ASIC pinout and pads.Synthesized and simulated integrated 3Soft 8051 core with RAM, ROM, and associated test logic in USB keyboard-controller chip. Test logic was created to allow testing of 8051, RAM, and ROM in 42-pin package using special test modes. Simulated/verified two generations of USB keyboard-controller chip and maintained the simulation envronment. Designed DMA interface for SCSI controller chip.

Evaluated vendor tools and libraries (Synopsys and Concept schematic) to select a gate-array vendor for the ISBGA ASIC to be used in the Attitude and Articulation Control System of the Cassini spacecraft. Translated the ISBGA ASIC from UTDR library to UTER library using Synopsys Design Compiler and performed static-timing analysis. Translated test vectors from Rapidsim simulation environment to Cadence Verilog/Verifault simulation environment. Performed pre-layout and post-layout simulation with Valid Logic Workbench.Implemented boundary scan (JTAG 1149) and full internal scan for testability using Synopsys Test Compiler for ISBGA. Developed custom test protocol for initialization of chip test pins and JTAG logic to sensitize internal scan paths for operation during ATPG. Fault simulated functional vectors and incrementally generated scan vectors using Test Compiler to meet target of 98.5% stuck-at fault coverage. Created and simulated vectors to test boundary scan logic. Wrote AWK program to calculate toggle coverage and to pick stop points for Iddq test using Verilog VCD file as input.Modified Power Distribution Assembly (PDA) ASIC to implement internal scan. Created and simulated PDA test vectors to perform functional verification using Orcad. Translated Orcad vectors and simulated in Mentor Quicksim with pre- and post-layout timing to verify functionality of the PDA. Wrote additional test vectors to meet fault coverage requirement of 98.5% for PDA. Ran fault simulation on Zycad logic/fault acceleration engine to verify final fault coverage.