Jeffery Chen work email
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Now working in Phison as SRAM designer, and I am also responsible for specific application IP design. 1. 1.2HGz PLL for SRAM system clock.2. Ring OSC based process sensor to monitor wafer process variation3. Customized Power Switch to balance IR drop, leakage and area.Previously, I have 7.5 years experience in analog circuit design, especially focus on various type of data converters(ADC/DAC), PLL and fundamental analog block, like OP, Bandgap reference. I also have experience in advanced FinFet process design and layout technique. I am a responsible person and like to take challenge. In addition, I have good interpersonal skills, as well as crosslingual communication competence in both Chinese and English. If you want to contact me, here is my email: skylifedestroy@gmail.com
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Field Technical SupportTsmc May 2022 - PresentHsinchu City, Taiwan, Taiwan -
Technical LeadPhison Electronics Corps. Mar 2018 - Apr 2022Hsinchu County/City, Taiwan1. Phison SRAM design and maintain in different process node.2. TSMC 12nm 1.2GHz PLL design for SRAM clock3. Ring Oscillator based process sensor design.4. Experienced in finfet process circuit design and layout.5. Directly work with EDA vendors to improve SRAM design flow.6. SRAM yield improvement, voltus-fi/customsim EMIR flow building.7. SRAM Aging simulation flow building for reliability evaluation. -
Senior Analog DesignerGuc Aug 2014 - Feb 2018Hsinchu County/City, Taiwan1. 3 .5years experience in circuit design, especially focus on various type data converters and analog circuit.a. 12-bit 100MS/s pipeline ADCb. 12-bit 100MS/s pipeline ADC with OP sharing architecturec. 10-bit 1MS/s SAR ADCd. 12-bit 5MS/s resistor ladder DAC2. Fundamental analog block design, including OPAMP, bandgap, oscillator. 3. Experienced in TSMC 0.18um/65nm/55nm/28nm process4. Good communication and language skill in cross-department cooperation, like layout, testing, and back-end engineering 5. Directly working with customers to solve technical issue -
Senior Analog DesignerHiji High Tech. Apr 2015 - Jul 2015Oita, JapanThree months exchange program from GUC to HHT(Oita, Japan)1. Learn basic knowledge of automobile-related IC design2. Build relationship with Japan’s customer
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Advanced Analog DesignerFaraday Dec 2010 - Aug 2014Hsinchu County/City, Taiwan1. 3.5 years experience of IEEE 802.3 10M/100M Ethernet physical layer. 2. Analog part of system block design, simulation and measurement, which including OPAMP, bandgap reference, PLL, transmitter, pipelined ADC.3. Experienced in UMC 0.11um/90nm/55nm/40nm process4. Top level integration of analog block5. Create layout floor plan and work closely with layout engineering.6. Create EVB Board floor plan and work closely with testing engineering.7. Compile date sheet and application note of Ethernet PHY. -
Second LieutenantCompulsory Military Service, Taiwan Roc Nov 2009 - Oct 2010
Jeffery Chen Skills
Jeffery Chen Education Details
Frequently Asked Questions about Jeffery Chen
What company does Jeffery Chen work for?
Jeffery Chen works for Tsmc
What is Jeffery Chen's role at the current company?
Jeffery Chen's current role is deputy manager at tsmc.
What is Jeffery Chen's email address?
Jeffery Chen's email address is sk****@****ail.com
What schools did Jeffery Chen attend?
Jeffery Chen attended National Cheng Kung University, National Chung Cheng University.
What are some of Jeffery Chen's interests?
Jeffery Chen has interest in Exercising And Exploring New Things, Reading.
What skills is Jeffery Chen known for?
Jeffery Chen has skills like Analog Circuit Design, Analog Signal Processing, High Speed Interfaces, Linux System Administration, Unix, Simulations, Debugging, Ethernet, Circuit Design, Mixed Signal, Matlab, Analog.
Who are Jeffery Chen's colleagues?
Jeffery Chen's colleagues are Meng Zhe Yu, 王仲榆, 趙喬喬, Ramandeep Singh, Yi-Ren Liu, Li Kh, Wei-Chung Hu.
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jeffery chen
Taoyuan City -
Jeffery Chen
New Taipei City
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