Jeff Hare Email & Phone Number

Windham, Nh, Us

Windham, Nh, Us

Us

EZFramePlus.com Boat Top Frame Design ApplicationCustom Marine Canvas Design and FabricationMarine Industry Launch & Haulout Software SolutionsMarina IT Consulting Services

Raleigh, Nc, Us

Full Stack .NET Architect/Lead Developer, Mentor, IT DevOps manager

Aliso Viejo, Ca, Us

Key developer on Lotus Notes Migrator for SharePoint product. Designed and Implemented a document migration platform for converting Lotus Notes documents into high fidelity OpenXML (MS Office) and PDF documents. Researcher, Architect and Project leader for the new line of Quest Software/Dell database migration tools based on WPF/MVVM & EF5.

San Jose, California, Us

Responsible for leading the UI development effort to enhance and maintain Allegro PCB-SI (Signal Integrity), Model Integrity librarian and SigWave graphical waveform viewer products. Instituted modern development techniques to improved product stability and overall quality. Wrote functional and design specifications for new products and features. Implemented and integrated statistical analysis algorithms for high speed signal resonance detection. Designed an advanced interactive graphical analysis application to analyze PCB layer stackup, materials and routing layer assignments.

Joined in early startup phase, helped define the product architecture and testing strategy. Synchronicity designed Configuration Management and Version Control systems for Electronic Design Data and Intellectual Property.Designed and Implemented solutions in C++/Java/TCL in the DesignSync & ProjectSync Configuration Management products.Designed and Implemented a specialized N-way graphical file diff/merge application. Designed and delivered the internal messaging & interrupt subsystem that permitted the multi-threaded core to interact with the UI in the single-threaded areas of code. Worked in a development and/or consulting capacity on nearly all the engineering projects within the company at various points since the company was founded.

PowerView Group: Architect/Lead Developer of the ViewTime Graphical Static Timing Verification product. Implemented graphical display of clock and data delay paths. Numerous translators, back-annotation and process flow tools were written to help design engineers move data into and results out of these tools. PC Engineering Group: Assisted in porting the Viewlogic PowerView product line of circuit analysis tools to WinNT/Win3.1. Ported the ViewSim mixed Verilog/VHDL & Gate level logic simulator user interface from unix to PC. Implemented in Microsoft MFC Visual C++ 4.0. Designed and implemented numerous smaller graphical and non-graphical applications to help round out the product line.

Houston, Texas, Us

Project Engineer - Consultant to Corp. CAD (Hewlett Packard)Key member of the HP Design Library architecture group. Helped design the schema of the new HP corporate relational component database. Also helped design a more efficient design process, combining the new Database with the Mentor 8.x tool suite. Key alpha/beta tester of Mentor 8.0 product.Project Engineer - Signal Integrity Group (Apollo Computer)Responsible for specifying and implementing a signal integrity tool set to improve system reliability and time-to-market. I was the sole software developer in this group which consisted of three team members. Integrated Quad Design's Transmission Line and Crosstalk high speed signal analysis tools with both SECMAI and Mentor Graphics PCB Layout tools to allow analysis of PCB routing effects prior to fabrication. Developed board level back annotation and analysis programs. Software Engineer - PCB Analysis Tools Group (Apollo Computer)Responsibilities included design and implementation of custom PCB processing and analysis tools such as Layout / Electrical Rule checking. Net/Component placement modification, and various PCB database translators. Designed and implemented a Portable Design Data Interface (PDDI) in C++ to provide a common interface to electrical and physical design data that was CAD vendor. This permitted multiple PCB/ASIC/MCM designs (both logical and physical) to be loaded and assembled for viewing or system level analysis.

Designed and implemented numerous portable ASIC CAD tools on both Apollo and MS-DOS platforms. Author of the CSi Generic ASIC Design Kit, a set of integrated, technology driven tools and libraries for foundry independent ASIC design. Other tools include, simulation vector comparison and analysis tools, delay back-annotation, gate/diesize calculators, simulation vector translators, power dissipation analyzer, and Logic Design Rule Checkers. Actively participated in reverse engineering a 15k gate full-custom n-mos VLSI VAX Bus Interface Chip using optical and Scanning Electron Microscopes to re-implement in Seiko/SMOS standard cell technology.

Phoenix, Arizona, Us

Developed numerous custom process and task automation tools supporting full custom VLSI integrated IC layout running on CADDS II. Developed and maintained physical design rules verification software. Wrote device independent graphics application in Fortran under VMS to view and plot IC layout databases on the first color Versatec 72" electrostatic plotter.Completed 18 bipolar IC redesigns and 2 MSI full custom integrated circuit physical layouts.