Jeff Seaman Email & Phone Number

Crystal Shaping Department:Responsible for yield improvement, customer 8Ds, CpK/SPC improvement, and cost savings: * Improved process yields by 0.5-1.0% or $30K annually. * Reduced ingot sample costs by $80K annually. * Reduced acid consumption of $120K annually. * Designed and managed an acid wet bench IQ/OQ/PQ * Assisted CW Green Belt team to reduce scrap loss by 67%. * Redsigned area reporting formats to expose area Muda.

Crystal Growing (CZ) Department:Responsible for silicon ingot yield, productivity and product quality improvement. * Performed equip. IQ/OQ/PQ during 250% CZ capacity expansion. * Developed Red Phosphorus growing process producing first <1.5 mili-ohm-cm resistivity product capability for SUMCO. * Reduced dopant consumption and costs by $8K / month.

Polished Silicon Wafer (PW) Department:Responsible for polished wafer yield, productivity, and quality improvements while meeting operational budget. * Imprpved surface yield and reduced consumable costs resulting in a $144K annually. * Implemented recycled slurry and mounting method to reduce cost by $12K / month.

Polished Silicon Wafer (PW) Department:Coordinated a polished wafer expansion that introduced wax mounting technology to SUMCO and allowed a competitive edge to be maintained. * Managed a $5 million budget involving all aspects of the cleanroom layout design and polished wafer process line IQ/OQ/PQ leading to a 50% increase in total silicon wafer polishing capacity. * Developed silicon wax mount process line yielding 0.8 micron wafer flatness capability. * Supervised engineering process technicians and trained manufacturing operators responsible to operate the fab line.

Polished Silicon Wafer Department:Responsible for installing state of the art mounting technology improving the silicon’s dimensional metrics, allowing increased market penetration at a net lower manufacturing cost. * Procured equipment and performed IQ/OQ/PQ yielding an increase in topographical flatness yields of over 25% from historical levels. * Reduced consumables cost by $25K / month by eliminating expensive template fixtures. * Increased CpK metrics to allow DRAM market penetration through improved flatness capability. * Developed a wafer defect recognition system integral to the new fab line, reducing defect levels by 7%, accounting for a $16K reduction in monthly rework costs.

Polished Silicon Wafer Department:Responsible for polished wafer area improvements by increasing yields, understanding defect sources and building robust processes which protect the silicon wafers during processing. * Led crossfunctional team using DMAIC / Juran / Deming principles contributing to a 6% scrap reduction and $75K annual savings. Submitted 3 patent disclosures during this project. Team was invited to Florida Power & Light team recognition award. * Led quality improvement team responsible in reducing silicon wafer scrap by 33%, without any capital investment.

Bachelors, Mechanical Engineering

Activities and Societies: Co-op internship performed at local manufacturing plants: Southco Inc.; Bendix ECD Division.Submitted patent.

Associates Degree, Design And Drafting