Senior Asic/Fpga Verification Engineer
Current
Ibm Research (Creative Global Consulting)
Senior verification engineer on a novel AI processor project.
Feb 2024 - Present
AeroLeads people directory · profile
Jeff Shaffer Email & Phone Number
Senior System/ASIC/FPGA Verification Engineer
at
Mutt Logic, LLC
1 work email found
@muttlogic.com
2 phones found area 410
LinkedIn matched
✓ Verified Jun 2026
4 data sources
Profile completeness 100%
Current company
Role
Senior System/ASIC/FPGA Verification Engineer
Location
Westminster, Maryland, United States
Who is Jeff Shaffer? Overview
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Quick answer
Jeff Shaffer is listed as Senior System/ASIC/FPGA Verification Engineer at Mutt Logic, LLC, based in Westminster, Maryland, United States. AeroLeads shows a work email signal at muttlogic.com, phone signal with area code 410, and a matched LinkedIn profile for Jeff Shaffer.
Jeff Shaffer previously worked as Senior ASIC/FPGA Verification Engineer at Ibm Research (Creative Global Consulting) and Owner, Manager and Individual Contributor at Mutt Logic, Llc. Jeff Shaffer holds Ms Candidate, Computer Science from The Johns Hopkins University.
Company email context
Email format at Mutt Logic, LLC
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{first}.{last}@muttlogic.com
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AeroLeads found 1 current-domain work email signal for Jeff Shaffer. Compare company email patterns before reaching out.
Profile bio
About Jeff Shaffer
Senior verification engineer with extensive experience in system, ASIC and FPGA verification,augmented with years of production-level software development experience. Expert backgroundin packet-based communications, high-performance computing (HPC) processors, video & imagery and geospatial data. Technical innovator with expert hardware / software skills.Specialties: System, ASIC & FPGA verification, technical and people management, complex system and software design & implementation, business development.
Listed skills include Asic, Functional Verification, Verilog, Debugging, and 28 others.
Current workplace
Jeff Shaffer's current company
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11 roles
Jeff Shaffer work experience
A career timeline built from the work history available for this profile.
Owner, Manager And Individual Contributor
CurrentOwner, manager and individual contributor collaborating with a team of senior and highly-skilled software engineers, hardware engineers, functional design verification specialists and researchers to deliver development services to a number of small to large clients.
Apr 2003 - Present
Fpga Verification And Validation Engineer
Nasa Jet Propulsion Laboratory (Raytheon / Correct Designs)
Senior verification engineer for a civil space mission.
Aug 2022 - Feb 2024
Senior Asic Verification Engineer
Viasat / Effect Photonics (Correct Designs)
Senior verification engineer on a DSP/FEC IP for Open ROADM optical modem project. Developed random/constrained UVM test infrastructure and test suite for multiple macro-level and IP top-level RTL designs using a custom UVMF/UVM-based architecture.Setup a Jenkins/vManager-based automated regressions environment for the project.Ported the existing.
Jun 2021 - Jul 2022
Senior Asic Verification Engineer
Ibm Research (Collins Consulting)
Senior verification engineer on a novel AI processor project.Developed random/constrained UVM test infrastructure and test suite focused on on-chip core-to-core packet routing.Developed a load/execute infrastructure, allowing automated regression of software-based tests.Developed a C++ / SystemVerilog DPI software API, allowing real-time software runtime.
May 2020 - Jun 2021
Senior Software Engineer
Survae
Senior Software Engineer - Focused on software engineering in video & imagery and geospatial data.
Nov 2017 - Mar 2020
Engineer And Manager
Hardware and software development positions. Specialized in hardware logic verification, development methodology and development of software tools used in the hardware development process for hardware fault-tolerant system and high-performance I/O IC design. Technical and people management positions as well as focused technical roles.
Jun 1993 - Apr 2003
Engineer
Supercomputer Systems Incorporated
Hardware development positions specializing in hardware logic verification for I/O subsystems.
Sep 1990 - Feb 1993
Project Design Engineer
Megatek
Logic designer and project lead for a family of 3D graphics systems.
Jun 1987 - Sep 1990
Project Test Engineer
Wavetek
Hardware and software designer for a test equipment manufacturer.
Jan 1987 - Jun 1987
Test Engineer
Datagraphix
Hardware and software designer for a high-end printer manufacturer.
Jan 1984 - Jan 1987
2 education records
Jeff Shaffer education
Ms Candidate, Computer Science
The Johns Hopkins University
Bseet, Electrical Engineering
Devry University
FAQ
Frequently asked questions about Jeff Shaffer
Quick answers generated from the profile data available on this page.
What company does Jeff Shaffer work for?
Jeff Shaffer works for Mutt Logic, LLC.
What is Jeff Shaffer's role at Mutt Logic, LLC?
Jeff Shaffer is listed as Senior System/ASIC/FPGA Verification Engineer at Mutt Logic, LLC.
What is Jeff Shaffer's email address?
AeroLeads has found 1 work email signal at @muttlogic.com for Jeff Shaffer at Mutt Logic, LLC.
What is Jeff Shaffer's phone number?
AeroLeads has found 2 phone signal(s) with area code 410 for Jeff Shaffer at Mutt Logic, LLC.
Where is Jeff Shaffer based?
Jeff Shaffer is based in Westminster, Maryland, United States while working with Mutt Logic, LLC.
What companies has Jeff Shaffer worked for?
Jeff Shaffer has worked for Ibm Research (Creative Global Consulting), Mutt Logic, Llc, Nasa Jet Propulsion Laboratory (Raytheon / Correct Designs), Viasat / Effect Photonics (Correct Designs), and Ibm Research (Collins Consulting).
How can I contact Jeff Shaffer?
You can use AeroLeads to view verified contact signals for Jeff Shaffer at Mutt Logic, LLC, including work email, phone, and LinkedIn data when available.
What schools did Jeff Shaffer attend?
Jeff Shaffer holds Ms Candidate, Computer Science from The Johns Hopkins University.
What skills is Jeff Shaffer known for?
Jeff Shaffer is listed with skills including Asic, Functional Verification, Verilog, Debugging, Hardware, Fpga, Soc, and Ic.
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