Jeff M. Email and Phone Number
Jeff M. work email
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Jeff M. personal email
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Experienced Semiconductor IC Test Engineer with probe and final test development/bring-up/New Product Introduction/debug of various highly integrated SOC ICs, high speed Redriver (5Gbps) ICs, and custom ASICs including mixed signal analog devices. Experienced in full product cycle including hardware design and device characterization to high volume manufacturing. Experience bringing high volumes into production with multisite efficiency to reduce test costs. Experience with production hardware including various handlers, probers, and assembly hardware. Experience with test hardware design and implementation: board layout, signal integrity issues and compensations, and board characterization. Experience with Qualification of multiple processes. Proficiency with lab equipment including oscilloscopes, logic analyzers, programmable power supplies and others. Experience with latest test platforms Verigy/Advantest SmartScale/93K (SmarTest) and Teradyne Ultra-flex (IGXL).My core competencies include test program development, device characterization, production release, and yield improvement for ASICs, mixed signal, digital and high-speed (up to 5 Gbps) ICs, using the latest test platforms such as Advantest Smartscale 93K, and Teradyne Ultraflex. I have extensive experience with C, C++, and various scripting languages, as well as with lab equipment, signal integrity, and board layout. I am proficient with Unix/Linux shells, Perl, TCL, Python and data extraction and manipulation tools.
Valens Semiconductor
View- Website:
- valens.com
- Employees:
- 291
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Senior Test EngineerValens Semiconductor Mar 2024 - PresentRichardson, Texas, United States• Develop and implement methods for testing networking and communications mixed-signal Semiconductor Integrated Circuits.• Develop all test hardware (Probe card and Load board definition and design)• Develop test programs for the purpose of qualification, characterization and subsequent high-volume production of the IC’s.• Develop and document DFx requirements.
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Principal Test EngineerNxp Semiconductors Apr 2018 - Nov 2020Chandler, AzManaged and contributed to multiple projects simultaneously. As Lead I have managed and driven all test development across the team while meeting the customers schedule. This is direct contributor and management of the full project.Co-manage our network file servers for storage of bench and ATE data. Also this position requires mentoring and support as needed across all projects in the group. Support probe testing across products with Accretech 3000exe expertise for qualification sampling and training of other personnel in the group. -
Senior Test Product EngineerNxp Semiconductors Feb 2013 - Apr 2018Tempe, AzTest program development on the Advantest Smartscale and 93K (Verigy) for various custom IC interface products including a USB3.0 re-driver at 5Gbps, high speed (~5Gbps) muxes and host controllers for multiple protocols including SD, SDIO, MMC, CE-ATA. Responsible for complete product cycle including NPI (hardware design and planning), probe, package bring-up, characterization, qualification, and production release. Ongoing product/yield analysis, improvement and disposition is also performed.
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Final Test EngineerFreescale Semiconductor Mar 2010 - Nov 2012Austin, TxSenior Test Engineer• Developed final test software on Teradyne Ultraflex for production of high end single and multi-core microprocessors and SOC networking devices. This included the top end Cisco networking SOCs. • Worked closely with design, DFT, DFTE engineers to develop and debug ATE tests/patterns for JTAG, BIST, SCAN, ACSCAN and power. • Experience debugging PCI Express BIST, Serdes BIST, GMII patterns. -
Probe Team Test LeadFreescale Semiconductor Dec 2008 - Feb 2010Developed probe hardware and software on Teradyne Ultraflex, J973, J971 and Agilent 93000 test platforms for evaluation, characterization, and production of high end single and multi-core microprocessors and SOC networking devices. This includes the top end G4 and Cisco networking SOCs. • Worked closely with design, DFT, DFTE engineers to develop and debug ATE tests/patterns for JTAG, BIST, SCAN, ACSCAN and power. • Introduced and debugged three separate new devices in same calendar year including complete program development and bring-up, loadboard/probecard design, layout approval and checkout on ATE.
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Senior Probe Test EngineerFreescale Semiconductor Jan 2004 - Nov 2008Austin, TxDeveloped probe hardware and software on J973 and J971 test platforms for evaluation, characterization, and production of high end single and multi-core microprocessors and SOC networking devices. • Worked closely with design, DFT, DFTE engineers to develop and debug ATE tests/patterns for JTAG, BIST, SCAN, ACSCAN and power. • Complete program development and bring-up, loadboard/probecard design, layout approval and checkout.
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Test EngineerMotorola/Freescale Semiconductor 1998 - 2004Austin TxDeveloped probe hardware and software on J973 and J971 test platforms for initial debug and bring-up and production of high end single and multi-core microprocessors and SOC networking devices on various New Production Introduction (NPI) Projects. Wrote Burn-In software for various BI platforms and debugged patterns for both qualification/reliability studies and production.
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Engineering TechnicianMotorola Sps Jan 1993 - Dec 1998Created ATE test software for qualification programs and specialty programs such as soft error memory characterization for production devices and test vehicles on the Teradyne J971/J973 testers. Implemented and debugged Burn-in tests for qualification processes of PPC devices.
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Equipment OperatorMotorola Sps Jan 1989 - Jan 1993General Test Equipment Operator
Jeff M. Skills
Jeff M. Education Details
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Electrical Engineering
Frequently Asked Questions about Jeff M.
What company does Jeff M. work for?
Jeff M. works for Valens Semiconductor
What is Jeff M.'s role at the current company?
Jeff M.'s current role is ATE Test Engineering Lead | Hardware and Software, Verigy/Advantest/93K, Teradyne UltraFlex.
What is Jeff M.'s email address?
Jeff M.'s email address is je****@****nxp.com
What schools did Jeff M. attend?
Jeff M. attended The University Of Texas At Austin.
What are some of Jeff M.'s interests?
Jeff M. has interest in Science And Technology.
What skills is Jeff M. known for?
Jeff M. has skills like Ic, Semiconductors, Debugging, Dft, Test Engineering, Soc, Testing, Perl, Test Equipment, Silicon, Microprocessors, C++.
Who are Jeff M.'s colleagues?
Jeff M.'s colleagues are Oriel Fenigshtein, Evgeniy Makarov, Nelly E., Daniel Volynets, Arik Kalmanovich, Igor Opalinsky, Arthur Liao.
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1mlhealth.org
1 (320) 5XXXXXXX
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Jeff Wahlen
Performance Driven Healthcare Ltc/ Rcf And Snf Environmental Management & Project Management (Construction) ProfessionalGreenville-Spartanburg-Anderson, South Carolina Area
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