Jeff M. Email & Phone Number

Richardson, Texas, United States

• Develop and implement methods for testing networking and communications mixed-signal Semiconductor Integrated Circuits.• Develop all test hardware (Probe card and Load board definition and design)• Develop test programs for the purpose of qualification, characterization and subsequent high-volume production of the IC’s.• Develop and document DFx requirements.

Chandler, Az

Managed and contributed to multiple projects simultaneously. As Lead I have managed and driven all test development across the team while meeting the customers schedule. This is direct contributor and management of the full project.Co-manage our network file servers for storage of bench and ATE data. Also this position requires mentoring and support as needed across all projects in the group. Support probe testing across products with Accretech 3000exe expertise for qualification sampling and training of other personnel in the group.

Tempe, Az

Test program development on the Advantest Smartscale and 93K (Verigy) for various custom IC interface products including a USB3.0 re-driver at 5Gbps, high speed (~5Gbps) muxes and host controllers for multiple protocols including SD, SDIO, MMC, CE-ATA. Responsible for complete product cycle including NPI (hardware design and planning), probe, package bring-up, characterization, qualification, and production release. Ongoing product/yield analysis, improvement and disposition is also performed.

Austin, Tx

Senior Test Engineer• Developed final test software on Teradyne Ultraflex for production of high end single and multi-core microprocessors and SOC networking devices. This included the top end Cisco networking SOCs. • Worked closely with design, DFT, DFTE engineers to develop and debug ATE tests/patterns for JTAG, BIST, SCAN, ACSCAN and power. • Experience debugging PCI Express BIST, Serdes BIST, GMII patterns.

Developed probe hardware and software on Teradyne Ultraflex, J973, J971 and Agilent 93000 test platforms for evaluation, characterization, and production of high end single and multi-core microprocessors and SOC networking devices. This includes the top end G4 and Cisco networking SOCs. • Worked closely with design, DFT, DFTE engineers to develop and debug ATE tests/patterns for JTAG, BIST, SCAN, ACSCAN and power. • Introduced and debugged three separate new devices in same calendar year including complete program development and bring-up, loadboard/probecard design, layout approval and checkout on ATE.

Austin, Tx

Developed probe hardware and software on J973 and J971 test platforms for evaluation, characterization, and production of high end single and multi-core microprocessors and SOC networking devices. • Worked closely with design, DFT, DFTE engineers to develop and debug ATE tests/patterns for JTAG, BIST, SCAN, ACSCAN and power. • Complete program development and bring-up, loadboard/probecard design, layout approval and checkout.

Austin Tx

Developed probe hardware and software on J973 and J971 test platforms for initial debug and bring-up and production of high end single and multi-core microprocessors and SOC networking devices on various New Production Introduction (NPI) Projects. Wrote Burn-In software for various BI platforms and debugged patterns for both qualification/reliability studies and production.

Created ATE test software for qualification programs and specialty programs such as soft error memory characterization for production devices and test vehicles on the Teradyne J971/J973 testers. Implemented and debugged Burn-in tests for qualification processes of PPC devices.

General Test Equipment Operator