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@synopsys.com
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3 phones found area 626, 591, and 650
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Jeff Winston is listed as Principal ASIC Design Engineer, at Synopsys Inc at Synopsys Inc, based in Marlborough, Massachusetts, United States. AeroLeads shows a work email signal at synopsys.com, phone signal with area code 626, 591, 650, and a matched LinkedIn profile for Jeff Winston.
Jeff Winston previously worked as Principal ASIC Design Engineer at Synopsys Inc and VP Hardware Development at Orb Analytics / Federated Wireless. Jeff Winston holds Bsee, Msee, Computer Engineering from Cornell University.
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AeroLeads found 1 current-domain work email signal for Jeff Winston. Compare company email patterns before reaching out.
[Students - I have no hiring authority. If that is your interest in connecting with me, there's no benefit. Thank You! :-} ] 20+ years experience in hands-on development of large (multi-million gate) ASICs and FPGAs, including Architecture, Specification, RTL design, Verification, Synthesis, DFT, back-end netlist-to-GDS, FPGA prototyping, place/route, test program, etc., Over 18 tapeouts. 13 of last 15 completed ASIC designs had first pass success.Extensive experience with design and verification of DSP and processor-related IP, including FFT, wireless PHY development, LDPC, OFDM, xMSK, xPSK, Turbo enc/dec, channel emulators, HDMI video, A/V, audio sample filtering and playback; also experienced with DDR PHY, SoCs, ARM, ARC, MIPS, other CPUs, SoC/CPU peripherals, DDRx, (incl. DDR5) LPDDRx, serial and high-speed I/O interfaces (e.g., SERDES, I2C, etc.), others.Proficient at selection of ASIC/FPGA tools, IP, libraries, and back-end, foundry and supply chain vendors. Significant experience as liaison to variety of ASIC back-end vendors, both in US and overseas. Strong experience with IP selection, development, purchase negotiation, and integration.Experience with development, verification, and protoyping of designs targeted at large, and small, FPGAs including ARM-based SoC FPGAs (Altera & Xilinx). Languages/Tools: Verilog, VHDL, Perl, Python, TCL, C/C++, VCS, Modelsim, Spyglass, Quartus, Vivado, PrimeTime, Design Compiler, Mentor DFT, others.5 patents awarded related to lookup technology for networking.1 patent awarded for wireless technology
Listed skills include Asic, Verilog, Soc, Fpga, and 46 others.
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A career timeline built from the work history available for this profile.
Sunnyvale, California, Us
RTL Design, specification/documentation, implementation, unit verification, and debug of high-performance highly-configurable DDR3/4/5 & LPDDR3/4/5 PHY digital IP (ASIC & FPGA) for leading-edge semiconductor processes. Design team lead.
Concord, Ma, Us
Responsible for hands-on development of multi-million gate FPGAs \ (Architecture, Specification., RTL design, Verification, FPGA Prototyping, etc) for wireless and satellite communications products. (LDPC, FFT, xMSK, etc) for commercial and military customers. Also developed wireless channel emulator. Acquired by Federated Wireless, 3/2015.
Hands-on development (Specification, RTL, Verification) and back-end (Synthesis, DFT, TIming Closure, etc.) of multi-million gate ASICs.
Us
Hands-on development of multi-million gate ASICs (Architecture, Spec., RTL, Synth,Verification, DFT, etc). Closed 5/09
Us
Hands-on development of multi-million gate ASICs (Architecture, Spec., RTL, Verification, Synth, DFT, etc). Video & compression, UWB PHY, Gb SERDES. Also developed large scale FPGA prototypes and served as team lead.
Us
Hands-on development of multi-million gate ASICs (Spec., RTL,Verification, Synth, back-end, DFT, etc) multi-channel 802.11 a/b/g MAC/PHY, also 802.11n development.
Hands-on development of large ASICs (Architecture, Spec., RTL, Verification, Synth, DFT, etc). Network processors, development and back-end. Acquired by Conexant, Jan. 2000.
Hands-on development of large ASICs (Architecture, Spec., RTL, Synth, Verification, DFT, etc). Fixed wireless, proprietary MAC. Acquired by Lucent, Feb. 1999, then group transferred to NJ.
Carrollton, Tx, Us
Hands-on development of large ASICs (Architecture, Spec., RTL, Synth, Verification, DFT, etc). (Formerly Steinbrecher). TDMA, CDMA. Division retired 4/98.
Hands-on development of large ASICs (Architecture, Spec., RTL, Synth, DFT, etc). Development of multiple DSP chips for sound processing and reproduction. Acquired by Young Chang, August 1990.
Houston, Texas, Us
Architect & Team Lead for multiple generations of full-custom VAX CPU peripheral chips. Design, Specfiication, Verification, DFT, circuit design, IC Layout, Test, etc.
Quick answers generated from the profile data available on this page.
Jeff Winston works for Synopsys Inc.
Jeff Winston is listed as Principal ASIC Design Engineer, at Synopsys Inc at Synopsys Inc.
AeroLeads has found 1 work email signal at @synopsys.com for Jeff Winston at Synopsys Inc.
AeroLeads has found 3 phone signal(s) with area code 626, 591, 650 for Jeff Winston at Synopsys Inc.
Jeff Winston is based in Marlborough, Massachusetts, United States while working with Synopsys Inc.
Jeff Winston has worked for Synopsys Inc, Orb Analytics / Federated Wireless, Axis Semiconductor, Sicortex, and Radiospire Networks.
You can use AeroLeads to view verified contact signals for Jeff Winston at Synopsys Inc, including work email, phone, and LinkedIn data when available.
Jeff Winston holds Bsee, Msee, Computer Engineering from Cornell University.
Jeff Winston is listed with skills including Asic, Verilog, Soc, Fpga, Digital Signal Processors, Vhdl, Semiconductors, and Rtl Design.
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