Joey Chen Email & Phone Number

Mississauga, On, Ca

Santa Clara, California, United States

Part of the RISC-V CPU design team at Tenstorrent. Working on high-performance processor design.• Designed and integrated a security module in System Verilog that provides encryption/decryption used by the processor front end• Added disable and drain functionality to AXI and CHI interfaces, handled control signals that crossed different clock domains• In System Verilog, consolidated SRAM macros from various modules into one centralized location to enable easier access by the PD teams and customers for SRAM configurability • Architected a new arbiter for the power management RTL to allow configurability for grant types and rounds

Ottawa, Ontario, Canada

Ethernet IP Team at AMD (formerly Xilinx). • Designed and integrated a performance monitor into existing and new IP using System Verilog to evaluate and sort forward error correction (FEC) statistics of incoming Ethernet packets• Developed a Python-based framework for automating verification processes between emulated hardware designs on FPGAs and Ethernet packet injection testers• Integrated an AXI-S loopback FIFO into existing RTL designs to allow RX traffic to be returned via the network port with System Verilog

Austin, Texas, United States

Architecture/Design Team• Designed RTL for a synchronous multi-core messaging unit between a single master and multiple slaves over AMBA APB in System Verilog • Created coverage and reset/clock gating/peripheral/debug verification tests using System Verilog• Architected and designed a synthesizable ARM/RISC-V testbench wrapper in Verilog for standardized power/performance comparisons

Canada

ASIC Design Team for Ethernet IP/RTL• Implemented an Ethernet packet congestion monitor and data pressure relief mechanism in Verilog• Rearchitected and prototyped using Verilog, the pipeline of a traffic management engine using flop-based pseudo memories to enable 2x - 4x current performance and future scalability• Designed the RTL of a new hybrid caching system to enable high-performance low-cost Ethernet statistical counters using Verilog

Santa Clara, California, United States

Work Flow Optimization (WFO) Team• Programmed a Python CLI tool for triaging, analyzing, and storing logs for jobs submitted to LSF/Slurm• Used Flask and Kubernetes to create and host a back end for serving logs over web API • Used ReactJS to develop a front-end that tabulates, analyzes, and categorizes JSON log data

Ottawa, Ontario, Canada

Test Automation Script Writer. QA and Dev.

Mississauga

Hamilton, Ontario

SHAD fellow of SHAD McMaster 2019

Bachelor Of Applied Science - Basc, Computer Engineering

Waterloo Computer Engineering Student

Ib Diploma, Ib Program