Jen Warfel Email & Phone Number

Raleigh-Durham, North Carolina Area

• Schematic design, PCB layout review, VHDL FPGA design, debugging, lab testing, and documentation for embedded telecommunications hardware
• Kintex 7 FPGA/Vivado design with PCIe core, Uart cores, and custom logic.
• New component selection and schematic updates for existing product due to obsolescence issues

Raleigh-Durham, North Carolina Area

• Team lead for GUI design verification
• Wrote, reviewed, and executed manual and automated test plans written in xml with some PHP and bash.
• Reviewed requirements and provided feedback about the testability of the requirements.
• Assisted my manager in distribution of workload both in personnel and lab resources.
• Trained and facilitated training of new team members both local and remote.
• Facilitated communication between software development engineers and managers, my QA team, and other QA teams.

Same as Senior Member of Technical Staff at Oracle, above. Oracle acquired Tekelec in August of 2013.

• Schematic design, PCB layout review, VHDL FPGA and CPLD design, PSoC design, debugging, lab testing, and documentation for embedded telecommunications hardware
• Several Altera CPLD and Xilinx FPGA designs and debug.
• Multiple Cypress PSoC designs and debug.
• Designed power solutions for boards using POLs and Bricks.
• Worked on embedded boards with Intel chipsets.
• Designed an ATCA compatible backplane including test cards and test strategy.

Verilog FPGA design and verification