Jenna Mayfield Email and Phone Number
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Specialties:* Large, medium and small team engineering project leadership* Milestone-based project planning and management* Xeon SoC hardware design and verification* CPU pre-silicon validation methodology: simulation and emulation* Engineering talent development and hiring* Pre-silicon validation tools, flows and methodologies* Logic/validation hardware resource managementPrior experience with:* Microprocessor RAS (reliability, availability, serviceability) architecture, design and validation* Xeon RAS architecture* Itanium RAS architecture* Itanium firmware stack architecture, design and validation* C, C++ and Itanium assembly coding* CVS, SVN, git, and Perl* Linux and Microsoft Windows development* Linux kernel and device driver design* EFI/Tiano application design
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Soc Validation Engineering ManagerIntel Corporation Aug 2016 - PresentSanta Clara, California, UsManage large, medium and small teams of Xeon SoC CPU validation & integration engineers. Define and manage multi-purpose server CPU validation schedule and pre-silicon milestones. Coordinate local and remote development of validation strategies including RTL simulation and emulation test plans; steer development and execution of RTL simulation and emulation test content; coordinate cross-discipline validation planning including simulation, emulation, co-emulation and silicon; personnel career development and management; drive engineer and manager hiring; coordinate site-wide management collaboration & development activities. -
Tools, Flows And Methods Engineering ManagerIntel Corporation Apr 2014 - Jul 2016Santa Clara, California, UsManage team of CPU logic, validation & integration Tools/Flows/Methodologies engineers. Coordinate local and remote development of validation infrastructure configuration and functional model tools; manage infrastructure and development pipeline support for local front-end CPU development team; personnel career development and management.
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Validation Joint Team And Pre-Silicon Firmware CoordinatorIntel Corporation Sep 2013 - Apr 2014Santa Clara, California, UsDeveloped and managed pre- and post-silicon Validation Joint Teams for Fort Collins Design Center microserver CPU covalidation; responsible for arranging and maintaining engineer-to-engineer communication mechanisms and joint validation plans between teams in Fort Collins and Guadalajara. Initiated regular planning sessions between platform firmware and BIOS teams across the globe, CPU development team, post-silicon validation team, and CPU architects; tracked firmware platform milestones and aligned with pre-silicon CPU development milestones; influenced corporate-level project milestone definition based on project experiences.
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Site Mentoring Program ChairIntel Corporation Sep 2009 - Apr 2014Santa Clara, California, UsInitiated site-wide mentor matching program for individual contributors at all levels. Recruited mentors and educated managers, technical leaders, and ICs in the first year of the program; in subsequent years coordinated the matching of mentees with mentors who will provide effective guidance in desired development areas, and evaluated program for improvement and expansion. Outlined program and assisted another small Intel site in implementing a similar program.
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Interim Cpu Global Validation Engineering ManagerIntel Corporation Jun 2013 - Sep 2013Santa Clara, California, UsPerformed CPU pre-silicon global validation managerial duties including validation plan development and execution, project milestone planning, and personnel management.
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Cpu Ras Validation LeadIntel Corporation May 2011 - Sep 2013Santa Clara, California, UsResponsible for planning and execution of pre-silicon CPU uncore error protection validation and RAS feature validation for Xeon family microprocessors, as well as engineer staffing analysis and new project scoping for RAS validation work for a separate family of Intel microprocessors. Consultant for RAS flows and RAS validation best practices to two follow-on cross-site Xeon microprocessor design projects. Consultant for hardware and firmware error handling and error injection design for Xeon and Itanium family microprocessors. Regularly mentor other engineers in leadership and planning skills.
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Senior Firmware EngineerIntel Corporation Oct 2002 - May 2011Santa Clara, California, UsItanium PAL firmware design, specializing in microprocessor error handling in the firmware layers. Led small team of engineers in developing processor firmware core error handling, core error injection tools and system interface error injection tools for multiple generations of Itanium processors. Extensive post-silicon debug experience on internal and OEM partner servers utilizing Itanium PAL firmware. Consultant for pre- and post-silicon validation methods for hardware/firmware error handling and error injection, including memory RAS feature validation done by cross-site validation teams.
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Interim Technical Marketing Engineering ManagerIntel Corporation Jan 2009 - Feb 2009Santa Clara, California, UsPerformed Server Platform Technical Marketing managerial duties including OEM partner processor covalidation management, pre-production processor part allocation, technical document publication management, server Software Development Vehicle shipments, and OEM partner server power-on activities.
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Senior Software EngineerIntel Corporation Jun 1999 - Oct 2002Santa Clara, California, UsLinux operating system IA-64 support. Coded and debugged kernel-level fault handlers and OS TLB error handling algorithms. Atlas project contributor (multi-company effort to develop Linux kernel code for the Itanium processor family); coordinated cross-company project meetings and supported OEM engineers in on-site Itanium processor power-on activities.
Jenna Mayfield Skills
Jenna Mayfield Education Details
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University Of WashingtonComputer Engineering -
Naches Valley High School
Frequently Asked Questions about Jenna Mayfield
What company does Jenna Mayfield work for?
Jenna Mayfield works for Intel Corporation
What is Jenna Mayfield's role at the current company?
Jenna Mayfield's current role is Engineering Manager at Intel Corporation.
What is Jenna Mayfield's email address?
Jenna Mayfield's email address is je****@****tel.com
What schools did Jenna Mayfield attend?
Jenna Mayfield attended University Of Washington, Naches Valley High School.
What skills is Jenna Mayfield known for?
Jenna Mayfield has skills like Debugging, Processors, Microprocessors, Perl, Firmware, Computer Architecture, Device Drivers, Linux, C++, Itanium, C, Linux Kernel.
Who are Jenna Mayfield's colleagues?
Jenna Mayfield's colleagues are Rakshit M, Ming Yang, Satish Talasu, Kartikey Parmar, Dave Barrientes, 张聪聪, Tori Schultz.
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