With a strong background in VHDL and Circuit design I moved into the next challenge of the Compilable Array design: Developing a high performance SRAM compiler system supported by synthesis.

I developed the concept and started the prototype implementation of a XML based array compiler to enhance the flexibility and remove array design specific and technologydependencies.To enable a common array compiler a close cooperation of the Raleigh and the Boeblingen compilable array design teams was started. During this project I worked several weeks in Raleigh. Finally the compiler was implemented and is used by different server design teams in IBM for P & Z processors.To prepare the team for next level challenges - in 2013 I took the chance to work 3 weeks in Bangalore with new members of the 8T Compilable team in India/Bangalore.

For 6 days in a year I took the chance to work with students of the DHBW Stuttgart. During the laboratory tutorial they developed VHDL models and implements those into a FPGA.

To enable the array compiler for the IBM Power Processor design team an enhancement of the Registerfile Compiler to generate SRAMs (Compilables) was required and implemented.After the successfully development and implementation of the server 8T array compiler for the IBM Power7 chip I became the leader of this new Compilable 8T Array team. Started with P7 the team provides compilables to all of the next generation IBM Power processors and several processors based on the IBM Power architecture.

In 2002 I joined the IBM STG hardware R&D team developing the processor chips of the PS4 (Broadcast engine) and the XBox360. I was responsible for the development of a register file compile system. This system automatically generated dual port register files up to 4GHz core frequency and offers lot more agility and efficiency compared to custom register files design that was used before. My contributions here were: - logic development (VHDL) , - code development (SKILL, Perl) - growable register files methodology concept (prototyp)as well as multiple aspects of the circuit design work:- circuit design and layout implementation, - timing analysis and timing clean up - PD & logic verification As member of the global IBM Array team I joined workshops and design reviews in Austin and Raleigh.

I developed a synthesize-able 8bit Micro-controller, the concept for as well as the PCB design of a development and evaluation system for this. Goal of the project was to enable a customer to start early with a VHDL model of the uC only - but already in the final system of its application. As the ASIC becomes available it was plug’n play to switch to the real application hardware.The TAT of the customers development was dramatically reduced and the software development for the micro controller was started already with the VHDL model only.

Topic of my Diploma Thesis: „Sequencer for a mixed signal test system“. Finally I had to develop a main board that controls the programmable test flow used to evaluate custom CMOS mixed signal chips.Main units of the concept and PCB were a in system configurable ALTERA 10K FLEX FPGA and a MAX 7000 CPLD.