Jeremiah Coleman

Jeremiah Coleman Email and Phone Number

Researcher Phd Candidate @ Princeton University
Princeton, NJ, US
Jeremiah Coleman's Location
Princeton, New Jersey, United States, United States
Jeremiah Coleman's Contact Details

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Jeremiah Coleman personal email

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About Jeremiah Coleman

Pursuing a PhD at Princeton University in the Houck Lab focusing on developing novel quantum devices for the future of quantum computing hardware. With new materials and designs, I am creating protected superconducting qubits that intrinsically are isolated from environmental noise to increase the coherence of superconducting qubits. As graduate president of Princeton Students in Quantum, I help create a community of Princeton students that learn about the research in the quantum field, contribute to quantum open source projects and competes in quantum computing hackathons and challenges.

Jeremiah Coleman's Current Company Details
Princeton University

Princeton University

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Researcher Phd Candidate
Princeton, NJ, US
Jeremiah Coleman Work Experience Details
  • Princeton University
    Researcher Phd Candidate
    Princeton University
    Princeton, Nj, Us
  • Princeton University
    Researcher Phd Candidate
    Princeton University Sep 2021 - Present
    Princeton, Nj, Us
    PhD researcher in Houck Lab researching novel protected superconducting circuits and qubits. With new materials and designs, I am creating protected superconducting qubits that intrinsically are isolated from environmental noise to increase the coherence of superconducting qubits.
  • Qed-C
    Quantum Computing Benchmark Intern
    Qed-C Jun 2021 - Sep 2021
    Arlington, Virginia, Us
    - Developed an application based quantum computing benchmark protocol for quantum hardware in collaboration with various Quantum Computing companies such as IBM, IonQ and Honeywell- Designed an open-source repository of the benchmark protocol with dedicated readmes describing each quantum algorithm and how each are benchmarked- Pushed ~20,000 lines of code benchmarking canonical and hybrid quantum algorithms in Qiskit, CIRQ, and Amazon Braket
  • The Stanford Quantum Computing Association
    President
    The Stanford Quantum Computing Association Jul 2020 - Jun 2021
    -Developed 3 new committees focused on a High School Quantum Computing Initiatives, Quantum Conversations between academia and industry, and Stanford's first joint Quantum Computing Hackathon-Organized and taught an Open Source Quantum Computing Stanford course connecting students with mentors and open source quantum computing projects
  • The Stanford Quantum Computing Association
    Logistics Chief
    The Stanford Quantum Computing Association Jan 2019 - Jul 2020
    -Facilitated quantum programming workshops with Rigetti, Google and professors hosting for 100+ undergraduate and graduate students-Communicated with various quantum computing startups, companies and research groups for tours, quantum conferences and workshops for Stanford undergraduate and graduate students
  • Google
    Quantum Hardware Research Intern
    Google Jun 2020 - Sep 2020
    Mountain View, Ca, Us
    - Designed temperature controlled soldering jig for automated creation of new wiring systems - Developed handshake between python controlled chip design software and EM Simulation Software Sonnet, allowing any engineer to design a quantum chip and simulate it all through python code- Created ipython tutorial notebook creating Bell circuits and defying Bell’s inequality on Google’s Quantum Chip
  • Stanford Center For Professional Development
    Lead Operator
    Stanford Center For Professional Development Apr 2018 - Sep 2020
    Stanford, Ca, Us
    -Record up to 100 hours a quarter of audio and video for a series of engineering lectures through SCPD -Set up and manage a booth with four assorted cameras and a professional mixer four times a week
  • Micron Technology
    Dram Product Engineer
    Micron Technology Jun 2019 - Aug 2019
    Boise, Idaho, Us
    -Used a uM3 tester and cold probe to create new trends revealing failing bits at newly reached cold temperatures-Conducted over 100 hours of high temperature dielectric capability tests to characterize new dielectrics’ impact on read and write times and verify a model for the degradation of the dielectrics-Correlated 1000s of failing bits between two different DRAM testers (uM3 and C1D) to improve correlation of failing bits between Probe Department, Physical Failure Analysis Department and DRAM Process Department-Created multiple python scripts to correlate failing bits with different stress conditions and different background patterns, and to sort, organize and present failing bit data taken from Micron’s database
  • Stanford Nanofabrication Facility
    Technical Quality Engineer
    Stanford Nanofabrication Facility Oct 2018 - Jun 2019
    -Trained in dry etching with AMT 8100 Plasma Etcher for chemical etching of non-metal and metal wafers-Etched 10 wafers monthly while monitoring standard procedures used with AMT 8100
  • Stanford University School Of Engineering
    Applied Physics Researcher
    Stanford University School Of Engineering Jun 2018 - Sep 2018
    Stanford, Ca, Us
    -Researched fin cavity optomechanics with applications for a nanophone to measure picoscale SAWs in the Laboratory for Integrated Nano-Quantum Systems (LINQS)-Experience using oscilloscopes, vector network analyzers, creating optical circuits and simulating by finite analysis on COMSOL -Experimented and identified effective optical circuits to minimize power loss while monitoring the device response to optimize the coupling between the mechanical and optical system
  • Ucla Henry Samueli School Of Engineering And Applied Science
    Ee Researcher
    Ucla Henry Samueli School Of Engineering And Applied Science Jun 2016 - Aug 2016
    Los Angeles, California, Us
    High School Summer Research Program. -Researched the Quantum Anomalous Hall Effect by growing magnetic topological insulators with a molecular beam epitaxy (MBE) and reflection high energy electron diffraction gun (RHEED) for dissipationless devices-Gained research methodology and advanced the technology to create electronic devices that do not release heat

Jeremiah Coleman Skills

Leadership Public Speaking Research Teamwork Project Management Team Building Team Leadership Java Matlab Dry Etch Optical Microscopy

Jeremiah Coleman Education Details

  • Princeton University
    Princeton University
    Electrical And Computer Engineering
  • Stanford University
    Stanford University
    Engineering Physics
  • Stanford University
    Stanford University
    Economics
  • International Baccalaureate
    International Baccalaureate
  • Granada Hills Charter
    Granada Hills Charter

Frequently Asked Questions about Jeremiah Coleman

What company does Jeremiah Coleman work for?

Jeremiah Coleman works for Princeton University

What is Jeremiah Coleman's role at the current company?

Jeremiah Coleman's current role is Researcher Phd Candidate.

What is Jeremiah Coleman's email address?

Jeremiah Coleman's email address is je****@****ail.com

What is Jeremiah Coleman's direct phone number?

Jeremiah Coleman's direct phone number is +181839*****

What schools did Jeremiah Coleman attend?

Jeremiah Coleman attended Princeton University, Stanford University, Stanford University, International Baccalaureate, Granada Hills Charter.

What skills is Jeremiah Coleman known for?

Jeremiah Coleman has skills like Leadership, Public Speaking, Research, Teamwork, Project Management, Team Building, Team Leadership, Java, Matlab, Dry Etch, Optical Microscopy.

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