Director for the Systems Platform Software organization which develops F5’s new state of the art Kubernetes based tenant hosting platform SW in addition to supporting our legacy HW platforms generating 70+% of F5 product revenue. SPS has 150+ agile developers in 4 US locations and India creating the platform SW for F5’s new chassis/blade and appliance platforms. Using modern CICD pipelines for development, continuous test, and quality release delivery, F5’s fastest ramping new platform SW to date allows the network ops persona to distribute resources to BIG IP and other F5 tenants creating secure boundaries between the tenants but also allowing tenants to be given HW resources to support their application delivery and security requirements.

Director for BIG IP Core Dataplane Group including core network stack from driver layer to L7. CDG is an organization of 95+ engineers on Agile delivery teams working in release trains on both our traditional BIG IP product and our future modularization and Kubernetes offerings. Led CDG’s transition from a traditional waterfall development methodology to an Agile engineering organization. The Dataplane also referred to as the traffic management microkernel is the key IP for F5’s largest revenue generation flagship SW.

Manager of TMOS Diagnostics, Platform Hardening, Big IP Build, and Product Development Tools teams. The team’s large scope has a focus on horizontal embedded capabilities for BIG IP Network devices and services for developers of the traffic management operating system.Product development lead for current and future BIG IP releases tasked with ensuring the development team (300+) meet our customer commitments for functionality, quality, and release schedule.

Manager for a team of hardware debug and support engineers who love to enable customer innovation by keeping software development platforms up and running. Our job is to delight customers and provide the highest level of technical support.

Lead for defining debug strategy for complex SoCs. Assess last generation Design for Debug/Design for Validation features and architect new features based off of need for fast debug throughput. Delivered new debug architecture to allow concurrent time-correlated debug of firmware and software agents in the system that is critical for debug of SW, FW, and system optimization. Debug assessments include silicon digital and analog debug, firmware debug, power management debug, SW debug, customer and platform debug. Technical leader for a team of 10 engineers responsible for ensuring Design For Debug, Validation, and Test features and tool stack are validated pre-si, created validation tasks/timeline for the team, and for defining the tool strategy, platform-debug hooks, and post-si validation scripting environment. Lead entire post-si validation team (100+) for project power-on readiness, power on execution, fuse/SKU definitions, and post-si debug execution flow

Provide the Interface between Customers and Enginnering Team: Gather requriements, technical assesment of requriements, timeline planning, risk assesment and communication

Provide mentoring and leadership for engineers of different disciplines – Electrical Engineers, Mechanical Engineers, Signal Integrity Engineers, and Software Engineers. Drive team process improvements focusing on documentation and accountability based off of customer driven requirements, design (including Design for Validation/Design for Test), requirements driven validation, and test. Lead formalization of tool team/silicon team interaction by mentoring the creation of the tool interface document and interaction timeline. Continuously survey debug and post-si validation landscape to look for new tool opportunities that lead to technology path-finding activities and eventual products.

Establish and maintains memory observability roadmap for mainstream IA mobile, desktop, and server processors. Architect on-die observability solutions for memory controller and memory buffer validation and debug to provide the best coverage and most efficient mechanisms to take processors and platforms from power-on to production.

Delivered hardware for tools used to observe data on high speed data buses in state of the art platforms that allowed Intel to debug leading edge memory buses. Directed all memory probe signal integrity activities including defining simulation boundaries conditions, DOEs, and ensuring model correctness that led to formal documentation of probe and platform design rules. Ran working group focused on future bus probing architectures and PCB design and layout reviews, test, and validation of memory logic analyzer probes. Python and Perl scripting for automation of tests and C/VB coding for GUI development of Validation Tools.

Worked on next generation Itanium Processors. Designed and optimized transistor level library cells using timing and noise specifications, simulated designs for both the memory and clock design teams, including a design for a 128-bit rotator.

Faculty member responsible for syllabus and teaching 150-200 students, 12 to 20 years old, ballet pedagogy