Jerome Lazarczyk Email & Phone Number

Raleigh, Nc, Us

Raleigh-Durham, North Carolina Area

Lead product engineer for 75mm and 100mm LED SiC crystal growth process coordinating all process and yield improvements. Initiated many new project and yield management strategies: project matrixing, linear regression yield analysis, individual crystal yield tracking, defect characterization paretos, universal crystal comment log, community collaboration via shared merged data file for inputs / outputs. Key projects: 35% yield improvement BFX process.

Raleigh-Durham, North Carolina Area

I held 2 positions:[1] Lead engineer over various die separation processes (mount, saw, cleans, break, UV, stretch/transfer). Directed 2 engineers and supervised 9 technicians. Enhanced yield monitoring strategies by tool and product. Created NCM summary file. Managed 6 product transfers to outsourcing company. Key projects: XR260 cut depth (2% yield), tape measurement & shape recognition proliferation, Scepter injector PM (1% brightness).[2] Backend Quality Engineer - Owned product quality after sort and prior to shipment. Created SPC system to track area health, as well as a sampling system to monitor outgoing product quality. Created most process documentation and implemented training. Excursion management and disposition. Transferred backend quality systems to outsourcing company and trained that engineer. Area improvements: reduced particles ~10-20x (new air returns), $150k/yr (new cover sheet).

Albuquerque, New Mexico Area

Mar'02 – Dec'04 Integration Engineer - Responsible for 300mm logic process integration/health of passivation/C4/reflow/backside metal segments. Mentor for process issues, excursion investigation, and whitepaper coaching. Aided in 2 process transfers, including P1262 certification 5 weeks early. A key integration liason to 200mm virtual factory (VF) for critical C4 issues (delamination, leakage, bump residues). Project/team leader of multiple groups, including a VF team to improve assembly yield/reliability by increasing bump CD’s. Divisional Recognition Award for key integration support of UBM delamination task force highlighting UBM undercut shape and wrote UBM paper to fix the issue (>40% reliability fallout to near zero). Aug'99 - Feb'02 Flash Yield Engineer - Responsibilities: (1) primary yield analysis engineer for health of >5 products over 3 processes; (2) sole defect metrology engineer to ensure inline product health; (3) parametric engineer to investigate electrical test deviations. Project leadership of multiple teams, including product baselining (sort, e-test, assembly, scrap, defect monitors, and architecture) and defect metrology system transfer to Israel (yield tracking systems, near real-time VF trends, WEB-based defect atlas, key yield/defect metrology contact). Developed several yield comparison systems/methodologies. Honed skills: statistical analysis, structured problem solving, excursion dispo, and presentation skills.Jun'96 - Jul'99 AMAT P5000 Process Engineer - Sustaining owner of P62X & P601 Flash Tungsten/ILD/oxy-nitride CVD processes. Spec and PCS creation/ownership. Improved factory flexibility / capacity by >50% by qualifying additional tools, as well as establishing VF cross-processing capabilities. Enhanced quality as chair of Recipe Change Control Board. Divisional Recognition Award for co-implementing Tungsten backside etch removal (+5.5 ISO die yield, +20% availability, +85% run rate, HF contamination removal).

Integrated Circuit Design

Bachelor Of Science (Bs), Electrical And Electronics Engineering