Jerome Wang Email & Phone Number

Irvine, California, Us

- Design of Industrial IoT modular platforms for development and customers. These systems are FPGA based, flexible, adaptable, and enable fast response to new market opportunities. - Low cost consumer based IoT modules. These are application specific, low power, and are designed to address a unique function.- High speed board designs: Google project ARA GP Bridge Chip with UniPro. In Vehicle Infotainment with TC9560XBG PCIe or HSIC to Ethernet bridge.

Cambridge, England, Gb

Delivered an Engineering platform for post silicon SiRFStarV validation. On-board circuits included real-time power measurements, power supply sequencing/margining, low power isolation, MEMS (3-axis Gyro, Accelerometer, Pressure, Magnetic), SQIF, DDR3, USB, I2C, SPI, and UARTs. To fully validate our ASIC and its mult-function GPIO pins, a Spartan6 FPGA was used as a switch matrix. A PicoBlaze CPU in the FPGA controlled this switch. Additional tasks of the CPU included the collection and formatting of GNSS data, real-time current measurements and reporting, and unit remote control. The entire design, including hardware, RTL, design documents, and bring-up was completed in time for chip arrival. The board set is in active use to drive the SiRFStarV to production. Produced a feasibility R/D platform for GPS/GLONASS. The focus was to validate the benefits of a dual satellite system receiver. The system included two SiRFStar receivers for down conversion, one Spartan 6 FPGA for receiver control, and two ADCs to feed quadrature data to a Synopsys HAPS-52 board with dual Virtex 5 LX330 FPGAs. Another key risk was to profile system performance as we transition our ARM processor from parallel to serial memory. This is a potential 36 pin reduction, removes barriers for memory expansion, and reduced BOM and design costs. This work confirmed our next generation SiRFStarV GNSS receiver. These platforms are still in use for algorithm and software development as well as case studies for future generation GPS receivers.

Architected and designed a modular platform with multple Virtex 4 FPGAs for pre-silicon RTL verification. This system along with an ARM11, mobile DDR, and industry standard buses was the verification and software development foundation for our next generation of SOC ASICs. Our SiRFStar IV GPS receiver was also verified on this system. Introduced and designed the modular ASIC evaluation platform targeted to validate new silicon. The Virtex 2 FPGA based architecture is flexible and can route circuits to engage features specific to a chip function. The recent arrival of both the GSD4t and GSD4e receivers were tested on this hardware. This platform is standard issue to both hardware and software engineers company wide.Provided all Verilog RTL designs on the modular ASIC evaluation platform and contributed heavily in RTL port-to-FPGA for pre-silicon verification. Also was the only RTL designer for a FPGA based ATE tester with the goal of reducing chip test times by allowing up to 8 devices on a single pass. This challenging Virtex 4 RTL design operated at 8 channels with input sampling data rates of 600 MHz. Designed a platform that hosted the very 1st SiRFStar III GPS receiver. There was enormous time pressure but the hardware functioned flawlessly. Maintained a perfect track record of delivering first-time-working hardware.Continued with reference and developer designs as the many flavors of the SiRFStar III GPS receiver experienced exponential sales driving SiRF to a successful IPO followed with stock price at record highs. Every variant of GPS silicon or customer specification required new matching hardware. A trend was quickly emerging as I steered designs to be flexible and re-useable using FPGAs. Both the Spartan 3 and Virtex 2 families were heavily engaged-one as a low cost and profitable developer platform while the higher performance option was used for in-house engineering support.

- Designed a complex digital board for a wireless broadband application-Arraycomm’s I-Burst system. This design featured a Motorola PowerPC 740/350 MHz, twelve Motorola 56311/150 MIPS DSPs, and Quad Xilinx 1.5 million gate FPGAs. Each board is fully hot swap compliant and master capable.- Involved with a team of engineers in the design and directed the software and hardware integration of a complex 1.5 million gate FPGA. This design is now a standard IP library core available to customers. The FPGA significantly reduces both software and DSP complexities and slashes cost of implementation.- Completion of several digital boards for Wireless Local Loop. Each design scaled performance with cost. These range in performance from the high speed Digital Alpha processor to our current PowerPC CPU.- Designed, simulated, and tested many of the FPGAs for both WLL and the Personal Handyphone System (PHS) projects. These designs paved the way for the current generation of revenue producing products.

- Implemented a modem card to support a CDMA wireless digital loop in a telephony application. Some of the major components include eight XILINX 4008 FPGAs, a Motorola 68360 microprocessor, and Stanford Telecommunication Multi-carrier modulation ASICs.

Bsee, Systems And Signal Processing

Msee, Networks And Systems