Jerome Albert Email and Phone Number

Absolutely thrilled to discuss what we've been cooking here at HSV... Palladium Z3 platform offers 2X+ capacity over prior product generations, lot of hours have gone into taking this little beast from architectural concept all the way through production. This is the fruit of a collaboration across all Cadence Business Units involving 100s of hard working and passionate engineers working together to assemble this custom crafted ASIC packing lot of transistors and embedded macros...Really proud of all the team here.

As part of the Samsung Foundry FDS (Foundry Design Services) team, promoting Samsung technology to external customers, developing partnership with IP vendors to strengthen Samsung ecosystem, working on multiple programs across industry segments: automotive / networking / consumer. Helping clients build their solutions from architecture definition to tapeout (SOW / RFI / RFQ).

Partitionning / Clocking and Top Level RTL Integration on next Nexus 9K platform (25.6T / 12.8T) using a Fully Abutted / Physical Aware approach. Floorplan based Feedthrough insertion / Latency Matching / Chiplet Integration through D2D Interconnect.

7nm Server Tape out. Largest device ever produced at Qualcomm: 16 x 4 PCIe Lanes / 82 Custom ARM Cores built around a mesh structure / 8 DDR Channels.Chip to Chip Interconnect: A Low latency Point to Point interconnect targeting dual sockets applications. SoC Timing Closure on Centriq 2400 Server Processor family: first 10nm ARM based Server packing up to 48 custom cores / distributed L3 Cache / Segmented Ring Interconnect / 6 DDR4 Channels / 32 PCIE Gen3 lanes and much more...

Build the SoC STA team from the ground up: hiring and mentoring junior and senior individuals to perform their duties.Responsible for X-Weave / X-Gene timing closure. X-Weave is a 12x10Gbps LAN / WAN / OTN Framer Mapper device with built in FEC to satisfy the growing datacenter connectivity requirements. X-Gene solution is the first ARM64 (ARM v8.0) based Server on a Chip integrating all the interfaces present in the datacenter (compute / storage / networking / security)Developed top and blocks timing constraints across all mode / Performed timing closure across all corners. Responsible for flow development / automation. - Physical aware timing ECOs / Recovery. - Physical aware I/O budgeting. - Constraints Analyzer and Checker. - Cross Domain Check.

Developed top and blocks timing constraints on Packet Pro SoC based family.Timing closure across all major interfaces: - DDR2 / DDR3 up to 1600 Mbps. - PCIE / SATA / XFI / USB.

Hardware validation engineer on Power PC based SoC. Bring up using JTAG processor probe. Linux module development. Customer support. Verification lead over Packet Routing Switch fabric products.Verification was using a data centric environment based on VHDL adapter models and a C/C++ frames generation and checking tool (traffic flow integrity and flow control functions checking).

Synthesis scripts development part of TI OMAP platform. Performed Gate level simulation as well ATPG test patterns development.