Jeyakumar A Email & Phone Number

• Experience in Verilog RTL based IP design, simulation, synthesis and verification• Experience in SOC integration• Experience in AMBA/I2C bus protocols, MIPI, SD/MMC protocols.• Synthesis of FPGA/ASIC designs• Gate level netlist and timing simulations• Functional pattern generation and re-simulation• FPGA/Post silicon validation • DC/RC synthesis scripts• LINT checks• Advance CDC checks• Non-Resettable flop checks• RMM guidelines and synthesis techniques• Verilog behavioral modelingSpecialties: Tools:-Simulation - ModelSim, NC Sim, VCS, NC-Verilog and Aldec’s Active HDL, Synthesis - Design Compiler, RTL Compiler, Leonardo Spectrum, Synplify Pro and Quartus, Lint - VNCHECK and SpyGlassAdvanced CDC - 0-In CDCNon-Resettable flops - Jasper

Listed skills include Verilog Based Behavioral Modeling/Verification, Verilog Design/Simulation, Fpga/Asic Synthesis, Fpga/Asic Validation, and 10 others.