Jianwei Li Email & Phone Number

Shanghai

1. DDR5 RCD03 @6800( Samples to customer) Responsible for digital team manage and full chip architecture design2. DDR5 MCR RCD01 @10400 Responsible for digital team manage and full chip architecture design3. DDR5 RCD04 @7600 (Samples to customer) Responsible for digital team manage and full chip architecture design4. DDR5 MRCD02 @12800(to tapeout) Responsible for digital team manage and full chip architecture design5. DDR5 RCD05 @8400(To samples) Responsible… Show more 1. DDR5 RCD03 @6800( Samples to customer) Responsible for digital team manage and full chip architecture design2. DDR5 MCR RCD01 @10400 Responsible for digital team manage and full chip architecture design3. DDR5 RCD04 @7600 (Samples to customer) Responsible for digital team manage and full chip architecture design4. DDR5 MRCD02 @12800(to tapeout) Responsible for digital team manage and full chip architecture design5. DDR5 RCD05 @8400(To samples) Responsible for digital team manage and full chip architecture design Show less

Shanghai

ASIC Design engineer, 200908 ~ 201108 DDR3 register buffer and DDR3 load reduce buffer @2400(Mass production). Responsible for module design and at-speed test FPGA platform design.Senior ASIC Design engineer, 201108 ~ 201308 DDR4 RCD01/DB01 @2666(Mass production). Responsible for critical module design, full chip PT and at-speed test FPGA platform designASIC Design manager, 201308 ~ 202108DDR4 production1. DDR4 RCD02 @3200(Mass production)… Show more ASIC Design engineer, 200908 ~ 201108 DDR3 register buffer and DDR3 load reduce buffer @2400(Mass production). Responsible for module design and at-speed test FPGA platform design.Senior ASIC Design engineer, 201108 ~ 201308 DDR4 RCD01/DB01 @2666(Mass production). Responsible for critical module design, full chip PT and at-speed test FPGA platform designASIC Design manager, 201308 ~ 202108DDR4 production1. DDR4 RCD02 @3200(Mass production) Responsible for digital team manage and full chip architecture design2. DDR4 RCD02 with NVDIMM @3200(Mass production) Responsible for digital team manage and full chip architecture design 3. DDR4 RCD02 with PCIe @3200(Mass production) Responsible for whole chip manageDDR5 production1. DDR5 RCD01 @4800(Samples to customer and work well) Responsible for digital team manage and full chip architecture design2. DDR5 RCD01 @5200(Mass production) Responsible for digital team manage and full chip architecture design3. DDR5 RCD02 @6400(Mass production flow) Responsible for digital team manage and full chip architecture design4. DDR5 XXX RCD01 @8800( Samples to customer) Responsible for digital team manage and full chip architecture design Show less

Shanghai

1. Motion Compensation of MPEG2 Decoder project.2. Multi-port dram controller design and DDR2/3 IP evaluation