Senior Asic Design Manager
Current1. DDR5 RCD03 @6800( Samples to customer) Responsible for digital team manage and full chip architecture design2. DDR5 MCR RCD01 @10400 Responsible for digital team manage and full chip architecture design3. DDR5 RCD04 @7600 (Samples to customer) Responsible for digital team manage and full chip architecture design4. DDR5 MRCD02 @12800(to tapeout).