Jibin Rocha Email & Phone Number

Kochi, Kerala, India

Working on a RISC based Soc from RTL to GDS2 on Intel 18A technology node. Having a deep understanding on Synopsys tools and Reference Methodology (RM) flow. Standalone Physical verification flow creation incorporating several tools such as fusion compiler, calibre for creating merged OASIS, V2LVS for spice netlist extraction and ICV for Layout.

Bengaluru, Karnataka, India

Gone through the fundamentals of Digital Design, Verilog and various concept CMOS VLSI DesignImplementation and characterization of CMOS logic gates and estimating timing of various Standard cells using Siemens Tanner Tool.Gone through various concepts in Physical Design including Synthesis, Floorplan, Place and Route, CTS and timing closure using various.

Hyderabad, Telangana, India

Worked with iPDK team to develop PyCell codes for the backend structure of PDK mainly for Global Foundries.Practical exposure on working with Synopsys Custom Compiler tool.

India

Worked in a team as part of implementing a target detection algorithm known as Constant False Alarm Rate (CFAR) in an FPGA which is to be used in SONAR Beamforming.

Bachelor Of Technology, Electronics And Communication Engineering, 8.66

Higher Secondary Education, 8.8

High School, High School/Secondary Certificate Programs, 9.0