Ji Gu
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Ji Gu Email & Phone Number

Sr. Manager Silicon Design Engineering at AMD at AMD
Location: Shanghai, China, China 9 work roles 3 schools
1 work email found @amd.com LinkedIn matched
4 data sources Profile completeness 100%

Contact Signals · 1 work email

Work email j****@amd.com
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Current company
AMD
Role
Sr. Manager Silicon Design Engineering at AMD
Location
Shanghai, China, China
Company size

Who is Ji Gu? Overview

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Quick answer

Ji Gu is listed as Sr. Manager Silicon Design Engineering at AMD at AMD, a company with 16705 employees, based in Shanghai, China, China. AeroLeads shows a work email signal at amd.com and a matched LinkedIn profile for Ji Gu.

Ji Gu previously worked as Sr. Manager Silicon Design Engineering at Amd and Manager Silicon Design Engineering at Amd. Ji Gu holds Doctor Of Philosophy (Ph.D.), Computer Science And Engineering from University Of New South Wales.

Company email context

Email format at AMD

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{first}.{last}@amd.com
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AeroLeads found 1 current-domain work email signal for Ji Gu. Compare company email patterns before reaching out.

Profile bio

About Ji Gu

An engineer has great research and design experience in processor architecture, front-end digital circuit, and embedded system design, with particular exposure to low-power and high-performance design for embedded processors and memory subsystems. Also an experienced verification engineer of using SystemVerilog, Vera, and the associated frameworks (UVM, OVM and RVM) in block and system level verification of 802.11 WiFi (up to 11ac and 11ah).Specialties:CPU micro-architecture, RISC architecture (MIPS, ARM, PowerPC), CacheVerilog, VHDL, SystemVerilog, VERA, C/C++, PerlFront end RTL designASIC design and verificationFPGA prototypingHardware/Software co-designEmbedded programming

Listed skills include Embedded Systems, Asic, Verilog, Rtl Design, and 10 others.

Current workplace

Ji Gu's current company

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AMD
Amd
Sr. Manager Silicon Design Engineering at AMD
santa clara, california, united states
Website
Employees
16705
AeroLeads page
9 roles · 24 years

Ji Gu work experience

A career timeline built from the work history available for this profile.

Sr. Manager Silicon Design Engineering

Current
Amd

Shanghai, China

GPU SoC Design Verification, SoC Power Analysis and Optimization

Apr 2022 - Present

Manager Silicon Design Engineering

Current
Amd

Shanghai, China

GPU SoC Design Verification, SoC Power Analysis and Optimization

Oct 2020 - Present

Smts Silicon Design Engineer

Amd

Shanghai, China

GPU SoC Design Verification

Jun 2017 - Sep 2020

Asic Design Verification Engineer Consultant

Amd

Shanghai, China

Ethernet, MAC/PHY, Certitude

Sep 2015 - May 2017

Asic Engineer (Consultant At Qualcomm)

Perth, Australia

Development of verification environments using SystemVerilog, Vera, and the associated frameworks (UVM, OVM and RVM), mostly in block and system level verification of 802.11 (up to 11ac and 11ah) MAC's.

Aug 2012 - Jun 2015

Research Associate

Kyoto, Japan

Worked on embedded processor architectures and OS-based power management techniques for environmental energy-based systems. Work is focused on the design of dynamic energy scalable multi-core architectures, low-energy multitasking processor design, on-chip resizable cache hierarchies design and non-volatile memory design techniques.

Oct 2011 - Jul 2012

Research Assistant

Sydney, Australia

Design of low-power embedded RISC processors, application-specific instruction set processors and other processor based ASIC systems. Work includes design of processor datapath, pipeline control, and memory hierarchy for power and performance optimization. The designs are implemented at RTL level and power/performance are evaluated based on post-synthesis.

2007 - 2011 ~4 yrs

Research & Design Trainee Engineer

Netherlands

Industrial trainee and research engineer works in cooperation with NXP for embedded systems design. Work includes mapping SiliconHive processor cores onto FPGA for prototyping, partitioning the program source code for core mapping, and design of the on-chip shared memory.

2006 - 2007 ~1 yr

System Engineer

Shanghai

Development of billing subsystem for military clients for an independent and confidential bill processing. Work includes design of the modules for bill generation, bill clearance and data synchronization between the sub-billing system and the main billing system.

2002 - 2003 ~1 yr
Team & coworkers

Colleagues at AMD

Other employees you can reach at amd.com. View company contacts for 16705 employees →

3 education records

Ji Gu education

Doctor Of Philosophy (Ph.D.), Computer Science And Engineering

Processor architecture, Embedded systems, Memory subsystem, Low power, High performance, Hardware/Software co-design

Master Of Science (Msc), Computer Science

VHDL/Verilog RTL design, FPGA, Multi-core platform design

FAQ

Frequently asked questions about Ji Gu

Quick answers generated from the profile data available on this page.

What company does Ji Gu work for?

Ji Gu works for AMD.

What is Ji Gu's role at AMD?

Ji Gu is listed as Sr. Manager Silicon Design Engineering at AMD at AMD.

What is Ji Gu's email address?

AeroLeads has found 1 work email signal at @amd.com for Ji Gu at AMD.

Where is Ji Gu based?

Ji Gu is based in Shanghai, China, China while working with AMD.

What companies has Ji Gu worked for?

Ji Gu has worked for Amd, Lateral Sands, Kyoto University, University Of New South Wales, and Eindhoven University Of Technology.

Who are Ji Gu's colleagues at AMD?

Ji Gu's colleagues at AMD include Kalaiyarasan Meganathan, Callan Mcinally, Sundar Rangarajan, Akhila Nakhate, and Daniel Bankman.

How can I contact Ji Gu?

You can use AeroLeads to view verified contact signals for Ji Gu at AMD, including work email, phone, and LinkedIn data when available.

What schools did Ji Gu attend?

Ji Gu holds Doctor Of Philosophy (Ph.D.), Computer Science And Engineering from University Of New South Wales.

What skills is Ji Gu known for?

Ji Gu is listed with skills including Embedded Systems, Asic, Verilog, Rtl Design, Vhdl, Simulations, Fpga Prototyping, and Signal Processing.

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