Jim Devoy Email & Phone Number

System Architecture and Digital Design Consulting

In March 2008, ON acquired AMIS, including the Colorado Springs DesignCenter. I was Project Lead for a new mixed signal medical device for glucose monitoring. My initial responsibilities included working with Systems, Software, and Marketing on product definition. During development I was responsible for chip specification, defining verification methodology, chip verification plan , design for test, chip proto-typing using an analog test chip and a FPGA, technical leadership for design team of 8, scheduling, working with backend design groups, working with manufacturing test engineering, and RTL design of some portions of the design, including the clock generator, Flash TAP, and the top level. I also wrote system level tests using Cortex firmware. The design contained an analog front end with ADCs and DACs, an ARM Cortex M3, on board Flash, and various peripherals including USB 1.0, UART, SPI and I2C interfaces. For low power consumption multiple supply domains existed which were programmable for many low power modes of operation. Special circuits were designed to further lower digital dynamic current consumption and lower Flash read current consumption.

In July 2006, AMIS acquired the Colorado Springs Design Center from Starkey Labs. I was a Project Lead for a Digital ASIC for Starkey Labs. I was responsible for chip specification, task assignment, schedule, and management of a 6 person design team. I also designed some of the modules and was responsible for the top level design. I was the technical contact with the customer. In addition to first silicon deliverables, we provided a proto-type system, consisting of existing IC's, and a FPGA. The proto-type system included demonstration firmware. I was responsible for the proto-type system and ASIC acceptance testing and reports. I also interfaced with AMIS manufacturing, quality, and planning to move the device into production. The ASIC consisted of a programmable uController, EEPROM, and wireless interface. It was implemented in 0.18u technology and was ~200k gates and memory. Current consumption was 300ua at 1.2v.

I was the digital design lead. In this role I supervised up to 10 direct reports, including task assignments and performance reviews. I was also responsible for chip specifications for the digital portion of mixed signal hearing aid products. I also performed RTL design on various modules and top level designs. I worked with program management to schedule and track multiple projects. One chip set, consisting of an Audio Codec with EEPROM ASIC and a Fixed Algorithm DSP ASIC, was the core for a multi generation product family. The DSP ASIC had a design complexity of 100K gates. Chip set current consumption was less than 600 uA at 1.2 V in 0.18u technology. I also worked on a new generation hearing aid product consisting of two ASICs. One was an Audio Codec with a programmable uController, wireless interface, and various peripheral interface ports. The second ASIC was a multi processor DSP ASIC, tailored for audio signal processing. The DSP complexity was ~1M gates. The product current consumption was less than 1ma at 1.2V in 0.13u technology. The system was proto-typed with an analog test chip and a FPGA for digital sections and I was directly involved in this work. As hearing aid products are all battery based, low power consumption was always a requirement and I have experience in low power design techniques. I started a verification group and oversaw the development of a SystemC based design verification methodology. This verification methodology was used on the above mentioned DSP ASIC and resulted in a first pass success.

I was the local digital design engineer for a remote design center located in Colorado Springs. I was responsible for the design of digital portions of Mixed Signal Read Channel devices. I designed RLL Codecs, PRML based digital read channels, DVD read channels, and other support circuits. I was also responsible for analog design verification using Spice. The last project I worked on required my co-ordination of design activities between the Colorado, Japan, and India design centers. Texas Instruments acquired Silicon Systems in 1997 along with our remote design center.

my primary focus was to enable RTL and Synthesis methodologies into the digital design flow. I was directly involved in synthesis and backend interfacing to foundry on 2 projects. I was involved in the military and commercial avionics market segment.

I worked as a design and methodology engineer in the IC design group at Digital. The design group's focus was hard disk drive development. I was involved in multiple digital ASIC designs for disk drives. I also developed and supported a gate array design flow for designs done by other organizations at the Colorado facility. I worked on the evaluation and incorporation of Silicon Compiler technology into the IC design group.

This was a Co-Op position while I attended the University of Colorado at Colorado Springs. I was responsible for maintenance of a real time manufacturing work flow tracking and management software system.

SkillsSOC Architecture, Specification, and DesignIC Architecture, Specification, and DesignDigital DesignMixed Signal DesignDSP Design ImplementationDesign for TestExperience with embedded processors including the ARM Cortex M3 processor IPDisk Drive Read Channel DesignHearing Aid DesignLow Power Digital DesignVerilog & VHDL RTL DesignMultiple Supply Domain DesignXilinx FPGA DesignDesign Verification and Test Plan SpecificationsDesign Verification using Modelsim and SystemCAnalog Verification using SpiceSynopsys DCLab testing and debugProject LeadershipSupervision of direct reportsProject schedules and tracking