Jim Gainer Email and Phone Number

I am presently a part of a small team developing a 10G downstream/10G upstream PON demonstration system for the enterprise PON solution utilizing Xilinx Zync7000 FPGAs. Previously, I was the FPGA team lead working for the EU SARDANA research project. We implemented a 10G downstream/1.25G upstream PON utilizing Altera StratixIV GX FPGAs. I am also a team member that implemented and supports the GPON interface card for the MX IPTV system. The OIU7 uses a mixture of 4 Altera and Xilinx FPGAs connected to a Broadcom switch to support 4 GPONs. The card has been adapted by modifying the initial Verilog RTL code to serve the enterprise market. At the beginning of the IPTV program, I contributed to the system level design and partitioning for the MX and FITL systems.

I was responsible for the design and test of the FPGAs for a custom power convertor card for the MX ONU which contained a high voltage charge pump storage/discharge subsystem.I previosly was a member of small team the conceived and developed a simple 4 ONT PON system for the MX Platform. This was successfully deployed in a new development in Northern Virginia.

I was a member of the team that provided system support for the FITL system. This team developed card enhancements that allowed for retrofits and new deployments. I designed and tested several circuit boards and FPGAs in this role.

I managed a team of seven engineers that provided systems level design for wireline access. Our team interfaced with a globally based set of internal and external partners to provide the initial A-PON, the first standardized PON. Previously, I was a member of a design team responsible for systems level interfaces for the AccessNode TAC and IMC line test cards.

I was responsible for the design of the signaling and OAM processing card for a new 672 line DLC. The design utilized multiple CPLDs controlling AC and ACT logic and static RAMs. I also completed the firmware to implement the TR-08 interface to the local POTS switches.In a prior project, I was responsible for the research, design, development, and simulation of two gate arrays for two of the common cards in the RPI-96 DLC system.My initial responsibility was the development of the 8x24 Key System communications link and the call processing firmware for the line controller interface that was based on 6805 microcontrollers.

I was responsible for developing and field testing both the hardware and firmware for a new web printing press unit controller that allowed digital entry of print unit adjustments and dynamic control to maintain alignment.

I was responsible for the failure mode analysis of several cards that made up the Delco Magic which determined whether single failure faults were detected by the built in test hardware within the mission critical avionics computer.

I was responsible for completing the development of the ATE test fixture and test software for Head Up Display Line Replaceable Unit. I was able to complete the fixture and software before the scheduled customer delivery date.