Jiun-Ming (Jim) Hsu Email & Phone Number

VMware vSphere platform performance analysis

Performance modeling, analysis and optimization of new storage server platforms.Guided hardware/software design and tuning. Identified root causes of throughput and latency issues. Delivered significant improvement to the performance of new mid-range and high-end systems. Recognized as the go-to person for all new platform performance needs.Drove the development and adoption of new profiling methodology that provides more accurate and timely performance information. Built a CPU analysis model to better predict benchmark performance based on workload characteristics.

Developed analytical model to predict the performance of Itanium based NonStop server, which is a clustered server with parallel, shared-nothing database. Measured and analyzed compiler performance using SPEC CPU benchmarks. The analysis and projection results were critical to new server development and roadmap strategy. Became an expert in the Division in CPU and compiler performance.Designed two Itanium based CPU performance measurement and profiling tools. Successfully led a team of offshore engineers to implement the tools under tight resource and time constraints. Solved many difficult technical and non-technical issues.Led and completed the modeling and simulation of an InfiniBand adapter chip with half of the budgeted staff. Evaluated design alternatives and made performance improvement recommendations.Played key role in performance analysis and tuning of mixed query workload and workload management system in HP’s Neoview (business intelligence) server. Contributed to significant improvement of overall server performance.Developed efficient ODBC based query driver. Improved speed and functionality of performance measurements.Received three outstanding contribution awards.

Characterized I/O workload requirements of large commercial servers enabling more accurate performance projections.Investigated, modeled and simulated intelligent I/O subsystem design alternatives based on system area network, message passing, and global I/O. Provided expert guidance to product divisions.

Helped improve Itanium microprocessor performance by modeling, simulation and analysis of branch prediction and data cache design alternatives.

Helped speed up development of a massively parallel processors prototype (Vulcan). Developed the first prototype software environment to enable test and measurement of communication performance.Performed research on communication architecture of multicomputers. Published papers in IEEE journal and international conferences.

Ph.D., Computer Science

Measured and analyzed the behavior of parallel application programs. Designed hardware support to speedup message passing by 5 to 13.

M.S., Electrical Engineering

B.S., Electronic Engineering