Jimit Shah Email & Phone Number

Boise, ID, US

Boise, Idaho, US

Competitor Analysis: Analyzed competitor's DDR5, LPDDR5, and GDDR products to understand the industry trend on I/O circuit innovation, Sense Amplifier area along with understanding device performance. - Lead the team to develop machine learning based algorithms to perform competitor analysis and reverse engineering. This work saved ~5000 man-hour yearly.

Boise, Idaho, US

Characterization: Conducted bench testing and wafer/package analysis to evaluate performance and identify failure mechanisms. Designed characterization methods, and performance metrics, and provided root-cause analysis and solutions through niche access patterns, Analog/Verilog simulations, and circuit debugging, resulting in improved product.

San Diego, CA, US

• System Test Development: Designed automated test infrastructure and scripts to put hardware blocks such as CPU, GPU, Video, DSI, and interfaces such as CAN, PCIe, HDMI, and SDCard under stress at a system level.
• Scripting: Writing Python scripts to analyze the Vmin profile of the IC, to automate system processes for bulk testing, and data parsing.
• Data Analysis: Experience with statistical data analysis tools such as data power and optimal plus for wafer mapping, data mining, and defect mapping.
• Bring up and Production Testing: Experience with temperature IC validation, board bring-up, andtroubleshooting system-level issues.
• PMIC Configuration: Design controls for the board power rails by accessing the PMICs' internal registers through SPI to change rail voltages for the specific failure case.
• Integration: Responsible for integrating system functional tests and increasing system coverage from 62% to 92% for automotive chipsets, as part of a team of four.

San Diego, CA, US

• Worked closely with Salk Institute to record ECoG data from Marmoset at 30K Sample/Sec using SPI Interface on Zynq-7000 FPGA.
• Worked on an AXI interface between ARM and FPGA to create Synchronous FIFO and Asynchronous FIFO which enables the device to do handshaking in the multi-clock domain.
• Detecting the potential brain activity on FGPA(Zynq-7000) using ”Spike Detection Algorithm” and storing spike data in the BRAM. This algorithm includes designing of the data path, RTL coding and verification in Verilog.
• Parallelism technique reduced the power consumption by 30% than the reference design.

Garden City, New York, US

• Acquired knowledge of hardware architecture for Network Interface which reduces average latency of the packet up to 25.1% and has high speed compared to conventional design.
• Minimized downtime by 10% with actively monitoring network performance and power usage with BillCall and Sansay billing/switching tools.
• IP and port assignment of the customer on class-4, class-5 soft switches as per routing requirements.
• Reported technical challenges and proposed resolution strategies to senior management.
• Averagely saved firm’s 200$ revenue per day, by pro-active monitoring for routing negative margins.

Master Of Science - Ms, Computer Science - Machine Learning Major

Master’S Degree, Electrical And Computer Engineering

Bachelor’S Degree, Electronics And Communication