• Design high-quality electro-optical image sensors for applications in commercial, consumer, industrial, biometrics, bio-medical, space, military, surveillance, and security markets.• Design analog and digital blocks and run simulation to verify their functions.• Layout the blocks.• Design print circuit board and evaluation board.• Test and verify the designs and their products.

• Worked with design centers to implement customer designs from design specification to RTL/gate level simulation and verification by using CCPS for chip estimation, SpyGlass for lint and clock domain crossing check, ConMan/ConCert for design constraint generation and verification, PowerArtist for power analysis, Design Compiler for synthesis, PrimeTime for static timing analysis, LEC for logic equivalent check, and VCS/NC-SIM for simulation.• Help mix signal team to verify Toshiba IPs and prepared libraries for customers.• Debugged and resolved customer design issues related to Toshiba design flow and technologies.• Defined methodology and flow to integrate 3rd party EDA tools into Toshiba SoC design environment.• Developed PowerArtist and SpyGlass design kits that are used in Toshiba design flow for ASIC SoC and FPGA.• Led projects of “Reducing design turnaround time” and “Improve the efficiency of using SpyGlass”. Both received company president’s award. • Oversaw the coordination and preparation of Toshiba design kit releases in U.S.• Mentored junior engineers for Toshiba design kits development, updates and maintenances.• Supported customers with setup design and tool environments and helped them understand Toshiba technologies.• Generated 3rd party tool libraries for Toshiba design kits and assured the quality of Toshiba libraries. • Trained internal engineers and customers for Toshiba design methodologies and design kit usage.• Evaluated new 3rd party tools and technologies, and participated in EDA vendors’ programs.• Provided technical support to business units for customer design wins.

• Developed Synopsys, Motive, Verilog, and Ikos libraries for submicron technologies.• Verified customer’s ASIC circuits in logic/timing simulation phase in Synopsys, Verilog, Viewlogic, Motive, and Ikos design environments.• Designed test circuits and methodology to test the library cells’ functionality and timing.• Provided Synopsys, Verilog, Viewlogic, Motive, Veritime, Ikos technical support to customers and internal people.

• Implemented, enhanced, and maintained NEC CAD tool interface software, such as design rule checker, delay calculator, netlist generator, and back annotation converter.• Created symbol libraries and logic/timing simulation models for 3rd party EDA tools.• Guided customers through CAD tool performance problems; answered customer questions and recommended problem solutions; provided software technical support to NEC design Centers.• Assured the quality of NEC logic gate, RAM, and ROM libraries for ECL, CMOS, and BICMOS technologies.