Jim Lewis, the founder of SynthWorks, is an innovator and leader in the VHDL community. He has thirty plus years of design, teaching, and problem solving experience. In addition to working as a Principal Trainer for SynthWorks, Mr. Lewis is available for ASIC and FPGA design and verification, custom verification component development, and consulting. Mr Lewis prefers challenging verification problems that push his expert VHDL skills.Mr. Lewis is chair of the IEEE 1076 VHDL Analysis and Standardization Working Group (VASG) and is an active member in IEEE VHDL standardization efforts.Mr. Lewis is the architect and principal developer of Open Source VHDL Verification Methodology (OSVVM), a leading VHDL Verification Methodology. OSVVM's utility library provides similar capabilities to other verification languages, such as SystemVerilog + UVM, and OSVVM's verification component library provides common models such as Axi4 (Full), Axi4Lite, AxiStream, and UART. Mr. Lewis was previously employed with Zycad’s Protocol division where he worked as an on-site VHDL trainer, methodology consultant, and ASIC designer. As a representative from Zycad, he provided VHDL training, methodology consulting, and ASIC design for Lockheed Sanders in their development of 22 ASICs for the F22 program. On another assignment for Zycad, he worked as a VHDL trainer, Synopsys synthesis trainer, problem solver, and ASIC designer for SGS Thomson in their development of a Video Codec chip. In addition to other responsibilities, Mr. Lewis acted as an on-site focal point for resolving VHDL synthesis issues for both companies.Mr. Lewis was also employed by TRW where he designed ASICs, FPGAs, and worked as a member of their VHDL Methodology Development Group.Mr. Lewis, who holds a BSEE/BSCEE and MSEE from Purdue University, is a member of the IEEE and the Eta Kappa Nu, and Tau Beta Pi Honor Societies. Specialties: VHDL and its application to testbenches and synthesis. Focused effort on creating constrained random, coverage driven testbenches and verification data structures using VHDL.