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Jim Lewis Email & Phone Number
VHDL Verification Specialist, OSVVM author, VHDL Trainer, SynthWorks, IEEE VHDL Working Group Chair
at
SynthWorks
2 work emails found
@synthworks.com
3 phones found area 503
LinkedIn matched
✓ Verified July 2026
4 data sources
Profile completeness 100%
Current company
Role
VHDL Verification Specialist, OSVVM author, VHDL Trainer, SynthWorks, IEEE VHDL Working Group Chair
Location
Portland, Oregon Metropolitan Area, United States
Company size
Who is Jim Lewis? Overview
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Quick answer
Jim Lewis is listed as VHDL Verification Specialist, OSVVM author, VHDL Trainer, SynthWorks, IEEE VHDL Working Group Chair at SynthWorks, a with 2 employees, based in Portland, Oregon Metropolitan Area, United States. AeroLeads shows a work email signal at synthworks.com, phone signal with area code 503, and a matched LinkedIn profile for Jim Lewis.
Jim Lewis previously worked as Director of VHDL Training at Synthworks and Chief Architect at Osvvm. Jim Lewis holds Ms, Ee from Purdue University.
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Email format at SynthWorks
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{first}@synthworks.com
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Profile bio
About Jim Lewis
Jim Lewis, the founder of SynthWorks, is an innovator and leader in the VHDL community. He has thirty plus years of design, teaching, and problem solving experience. In addition to working as a Principal Trainer for SynthWorks, Mr. Lewis is available for ASIC and FPGA design and verification, custom verification component development, and consulting. Mr Lewis prefers challenging verification problems that push his expert VHDL skills.Mr. Lewis is chair of the IEEE 1076 VHDL Analysis and Standardization Working Group (VASG) and is an active member in IEEE VHDL standardization efforts.Mr. Lewis is the architect and principal developer of Open Source VHDL Verification Methodology (OSVVM), a leading VHDL Verification Methodology. OSVVM's utility library provides similar capabilities to other verification languages, such as SystemVerilog + UVM, and OSVVM's verification component library provides common models such as Axi4 (Full), Axi4Lite, AxiStream, and UART. Mr. Lewis was previously employed with Zycad’s Protocol division where he worked as an on-site VHDL trainer, methodology consultant, and ASIC designer. As a representative from Zycad, he provided VHDL training, methodology consulting, and ASIC design for Lockheed Sanders in their development of 22 ASICs for the F22 program. On another assignment for Zycad, he worked as a VHDL trainer, Synopsys synthesis trainer, problem solver, and ASIC designer for SGS Thomson in their development of a Video Codec chip. In addition to other responsibilities, Mr. Lewis acted as an on-site focal point for resolving VHDL synthesis issues for both companies.Mr. Lewis was also employed by TRW where he designed ASICs, FPGAs, and worked as a member of their VHDL Methodology Development Group.Mr. Lewis, who holds a BSEE/BSCEE and MSEE from Purdue University, is a member of the IEEE and the Eta Kappa Nu, and Tau Beta Pi Honor Societies. Specialties: VHDL and its application to testbenches and synthesis. Focused effort on creating constrained random, coverage driven testbenches and verification data structures using VHDL.
Listed skills include Vhdl, Fpga, Asic, Functional Verification, and 15 others.
Current workplace
Jim Lewis's current company
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Synthworks
10 roles · 41 years
Jim Lewis work experience
A career timeline built from the work history available for this profile.
Director Of Vhdl Training
CurrentCurrently heading up all engineering and marketing aspects of SynthWorks. We bring your engineers up to speed with FPGA design and verification. We have pioneered leading-edge verification techniques and share them with the VHDL community through our Open Source VHDL Verification Methodology, OSVVM, effort. We also support IEEE 1076 VHDL standardization efforts.
Jan 1997 - Present
Chief Architect
Current
Osvvm
I am the architect and principal developer of Open Source VHDL Verification Methodology (OSVVM), a leading VHDL Verification Methodology. OSVVM's utility library provides similar capabilities to other verification languages, such as SystemVerilog + UVM, and OSVVM's verification component library provides common models such as Axi4 (Full), Axi4Lite, AxiStream, and UART. OSVVM's utility library provides the VHDL community with advanced verification capabilities, including functional coverage, "Intelligent Coverage" (aka coverage driven randomization) test generation, constrained random test generation, verification data structures (Scoreboards, FIFOs, and Memories), Error Reporting and Message Filtering, process (thread) synchronization utilities, and transaction based modeling.
Jan 2012 - Present
Chair Of The Vhdl Standards Working Group
CurrentChair of the VHDL-2019 (1076-2019) effort. Proposed features and provided edits to the LRM to make them happen. Focused on improving protected types for creating better verification data structures and VHDL Interfaces. Invested 1000's of hours into this volunteer effort. Also supported the development of VHDL-2008 through both IEEE and Accellera. Late in that effort I became chair of the IEEE WG and administered the balloting effort for both the 1076-2007 amendment (added VHPI) and 1076-2008.
Dec 2005 - Present
Yoga Teacher
Jul 2015 - Oct 2015
Consulting Engineer
Consultant
VHDL based ASIC and FPGA design, simulation and synthesis.Supported Kentrox's IMA ATM board development. Designed components in the ATM data path. Targeted Altera 10K50 FPGA devices.Supported Intel's Netport product, a network print server. Designed Intel 486 interface for the ASIC.
Apr 1995 - 1998
Consulting Engineer
Qualis
Supported Intel's Netport product, a network print server. Designed DMA controller and enhanced IEEE 1284 Parallel Ports.
Jul 1994 - Apr 1995
Senior Systems Enginner With Protocol Division
Zycad
On-site consulting in VHDL methodologies for ASIC design and system simulation.Team member, trainer, and methodology consultant for Lockheed Sanders in their development of 22 ASICs for the F22 program. Gave training in VHDL synthesis and simulation. Designed an ASIC. Assisted with directory and library organization, development of multiple ASIC simulations, and development of reusable testbench models.Team member, trainer, and VHDL consultant for SGS Thomson in their development of a Video Codec. Gave training in VHDL coding for synthesis and synthesis strategies with Synopsys tools. Designed, simulated, and synthesized several pieces of the ASIC. Became a site focal point for VHDL synthesis issues.
Dec 1992 - Jun 1994
1986 - 1992
~6 yrs
Co-Op Engineer
Worked for non-destructive test group. Designed DMA image capture board. Programmed in assembly language.
Sep 1981 - Aug 1984
1 education record
Jim Lewis education
-
Purdue University
FAQ
Frequently asked questions about Jim Lewis
Quick answers generated from the profile data available on this page.
What company does Jim Lewis work for?
Jim Lewis works for SynthWorks.
What is Jim Lewis's role at SynthWorks?
Jim Lewis is listed as VHDL Verification Specialist, OSVVM author, VHDL Trainer, SynthWorks, IEEE VHDL Working Group Chair at SynthWorks.
What is Jim Lewis's email address?
AeroLeads has found 2 work email signals at @synthworks.com for Jim Lewis at SynthWorks.
What is Jim Lewis's phone number?
AeroLeads has found 3 phone signal(s) with area code 503 for Jim Lewis at SynthWorks.
Where is Jim Lewis based?
Jim Lewis is based in Portland, Oregon Metropolitan Area, United States while working with SynthWorks.
What companies has Jim Lewis worked for?
Jim Lewis has worked for Synthworks, Osvvm, Ieee, Turtles Yoga & Wellness, Llc, and Consultant.
Who are Jim Lewis's colleagues at SynthWorks?
Jim Lewis's colleagues at SynthWorks include Jim Lewis.
How can I contact Jim Lewis?
You can use AeroLeads to view verified contact signals for Jim Lewis at SynthWorks, including work email, phone, and LinkedIn data when available.
What schools did Jim Lewis attend?
Jim Lewis holds Ms, Ee from Purdue University.
What skills is Jim Lewis known for?
Jim Lewis is listed with skills including Vhdl, Fpga, Asic, Functional Verification, Simulations, Altera, Testing, and Integrated Circuit Design.
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