Memory IP Analog Circuit design1. responsible for design of Low Power Bulk-Driven Amplifier2. run wafer test and collect data of SST ESF3-55 Memory Cell 3. Ultra Low Power Memory IP Sense Amplifier Design and Analysis

Participating in the design and simulation of flash chip with 90nm NOR FLASH process. Mainly be responsible for: 1) power on block design optimization and simulation; 2) On chip oscillator (80 MHz) optimization and simulation; 3) Charge Pump simulation; 4) Write protect logic design and verification; 5) Test Mode optimization and simulation analysis; 6) Program, Erase and Read simulation of the chip Logic State Machine. This design was taped out and is under testing and debugging at… Show more Participating in the design and simulation of flash chip with 90nm NOR FLASH process. Mainly be responsible for: 1) power on block design optimization and simulation; 2) On chip oscillator (80 MHz) optimization and simulation; 3) Charge Pump simulation; 4) Write protect logic design and verification; 5) Test Mode optimization and simulation analysis; 6) Program, Erase and Read simulation of the chip Logic State Machine. This design was taped out and is under testing and debugging at present. Participating in the testing flow of the 90nm chip. Participating in circuit design with 65nm NOR Flash process. Mainly be responsible for: 1) BandGap circuit optimized design and simulation analysis; 2) Build part of the Standard Cell Library; 3) Verilog HDL design of Address Buffer Logic circuit. Show less