Jinwoo Bae Email and Phone Number
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EMBEDDED HARDWARE - RTL development : Arithmetic, shift, relational, equality, bitwise, reduction, logical and / or, concatenation, conditional, always block, if & case statement, counter, define parameter and constant - FPGA serial interface : SDLC(NRZ, NRZI), SPI, I2C, UART - FPGA bus interface : Address-Data bus, VME bus - Customize IP Cores : DCM, FIFO, Dual Port Ram - Manage the memory map between FPGA and CPU - Synchronous & asynchronous interface handler - VUnit for verification test bench : Ethernet packet generator and checker to evaluate system level test - Real-time debug - Sensor signal gain control circuit - LPF, HPF, BPF, Anti-Alias Filter circuit - Ethernet interface circuit - Debug and verify tool : Oscilloscope, function generator, power supply, logic analyzer, peak power meter, digital multi meter, soldering kitEMBEDDED SOFTWARE - Sys Ctrl : Set the PLLCR, PLLSTS - XINTF : Set the address / data / significant control lines of external zone 0, 6 and 7 - PIE Ctrl : Set the Interrupt Flag and Enable 8 external interrupt lines - PIE Vector Table : Set the External Interrupt / SPI / SCI / I2C lines - Boot Mode : FLASH BOOT MODE, SARAM BOOT MODE - Real-time debug by using Watch Window and Real Time Mode DebugDSP - Common Programming skill : Interrupt handler, under & over flow memory handler, volatile, structure and union, two-dimensional array, DMA read & write, Virtual Memory read & write - TCP/IP, UDP, RS-232, SPI, USB - Algorithms by using IPP Libraries : Sonar Signal Process - Zigbee protocol by using Z-Stack : CSMA-CAMATLAB & Simulink - MATLAB function to design Sonar Theory - Reporting program : Import and verify .csv file - PID Control Loop : Current, Speed, Position Loop of BLDCAuthorized work in U.S.
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Sr. Actuation Engineer - Motor ControllerSupernal Apr 2024 - PresentWashington, D.C., Us
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Sr. Embedded Sw EngineerAibot May 2023 - Apr 2024Long Beach, California, Us -
Sr. Fpga Design Engineer, AvionicsVirgin Orbit May 2022 - Apr 2023Long Beach, Ca, Us -
Sr. Electronics EngineerSafran Oct 2018 - May 2022Paris, Fr• BLDC Motor Control Algorithm : Bipolar BLDC Motor control include current, speed, and position loop• Implement PI control model to Motor Control logic by using C Code Generation.• Design Brushless Permanent-Magnet Machine by using Altair Flux, Flux Motor• Develop 300 Watt PFC circuit -
Electrical EngineerZodiac Aerospace Feb 2018 - Oct 2018Plaisir, Fr• BLDC Motor Control Algorithm : Bipolar BLDC Motor control open loop• Memory Map verify and debug between XE167 and SRAM -
Sr. Electronics EngineerRje International, Inc. Apr 2017 - Dec 2017Irvine, Ca, Us• Target Device : SAM D21G18A, Spartan 6, PGA460-Q1, CC2500, MMA8451Q, IS31FL3731, 128x128 OLED, GPS Module• Development Tool :ATMEL STUDIO7, Arduino, ISE 14.1, PGA460-Q1 EVM• DSP Development and Demonstrate : DFLL 48Mhz, 32-bit Timer Counter Compare/Capture, Event, Interrupt Handler, SPI, I2C, ADC, Measure Distance and Angular algorithm, Sync algorithm between Transmitter and Receiver, Generate the accurate 1 second event• FPGA Development and Demonstrate : Generate the accurate 1 second event, Measure Distance and Angular Algorithm. Sync Algorithm between Transmitter and Receiver -
Research EngineerLig Nex1 Jan 2014 - Sep 2016Yongin-Si, Gyeonggi-Do, KrBefore launching a guided missile, it is necessary to test and verify the integrity of the guided missile system. I was solely responsible for developing the guided missile simulator to test and evaluate 1) the analog and digital signal between the VLS (Vertical cold Launch System) and the missile and 2) the telekit (RF) signal between the MFR (Multi Function Radar) and the missile.Develop Missile Simulator System• Target Device : Spartan6, TMS320F28335, W5300• Development Tool :ISE 14.1, Chip Scope, Code Composer Studio 5.5• FPGA Development and Demonstrate : CPU Address-Data Interface, SDLC Interface(NRZ / NRZI), Signal Process Sync Logic, FIFO Driver, System Algorithm• DSP Development and Demonstrate : External Address-Data Interface(Zone0), SCI, Interrupt Handler• Board design, Debug BoardDevelop Evaluate Tool by using Matlab• Import *.csv file which was saved after launching test. • Evaluate the *.csv file by comparing with ICD(Interface Control Document)• Automatically generate a result of *.csv file with report format. -
Embedded Software EngineerMarine System Technology Oct 2012 - Dec 2013Due to shallow water levels in the Yellow Sea, it is not an easy environment in which to employ sonars. This project entails the installation of sonars on both sides of the ship’s hull so that the sonars could be employed at all times. I was responsible for developing the Sonar Signal Process. This system successfully exceeded all of the military’s expectations and requirements.Signal Processor System•Target Device : Intel Core i7-2715QE•Development Tool :IPP Libraries 5.2, Measurement Studio•VxWorks Development and Demonstrate : Interpolation Process, Delay and Sum Process, Decimation Process, Environment Noise Estimation, Narrow Band Demon, LOFAR, VERNIER ProcessSONAR SIGNAL PROCESSING(using IPP Libraries)•Beamforming, Interpolation, Decimation, Delay and Sum, Chebyshev filter, Kalman filter, S3PM window, OTA window Environment Noise Estimation, Narrow Band Demon, LOFAR, VERNIER•Speed of sound in water is 1500m/s •PL (Propagation Loss) = SL (Source Level) + TS (Target Strength) – N (Noise) + DI (Directivity Index) + 10logT – 5log d (Passive Sonar Equation)•Sound Speed Profile•Reliable Acoustic Path (RAP) & Shadow Zone
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Electronics EngineerUnitech May 2007 - Mar 2012Detect the Red Tide and Jellyfish(08.2011 – 03.2012) •Target Device : Spartan6, S5PC100•Development Tool :ISE 13.1, Chip Scope•FPGA Development and Demonstrate : CPU Address-Data Interface, AD7685 SPI, Signal Process Sync Logic, FIFO Driver, System Algorithm•Linux Development and Demonstrate : External Bus Interface Driver, I2C Interface Driver, SPI Interface Driver, SD Card Driver, RS-232 Interface Driver•Board design, Debug BoardSRSN(Surveillance and Reconnaissance Sensor Network) Sensor Node (05.2007 – 08.2011)•Target Device : Virtex-5, Virtex-4, Spartna6, Spartan3, TMS320F28335, TMS320F2812, LM8738, PXA270, PXA255, CC2431•Development Tool :ISE 8.2i to 12.1, Chip Scope, Code Composer Studio 3.3, IAR 5.50, Fedora, •Board design, Debug Board•FPGA Development : DSP Address-Data Interface, AD7193 SPI, ADS1274 SPI, PGA2505, FIFO Driver, System Algorithm, ADS7734 SPI, AD5242 I2C, DSP Address-Data Interface, AD7685 SPI, FPGA Driver, DAC Interface, PXA270 Address-Data Interface, AIC23 SPI / PCM, PXA255 Address-Data Interface•DSP Development : External Address-Data Interface(Zone0), SPI Interface with McBSP-A, SCI, I2C, UDP Interface Driver(Zone6), Gain Setting application, Sensor Signal Algorithm•IAR Development and Demonstrate : RF Wireless Network Interface•Omni condenser microphone, Dynamic microphone, Accelerometer, Magnetic, PIR, Humidity, Digital CompassP-3CK(03.2009 – 05.2010) •Target Device : Spartan3, PXA270, PCI-6221(National Instruments)•Development Tool(Verilog HDL) :ISE 10.3, Chip Scope, Fedora•Board design, Debug Board•Tacco, NAV/COMM, Acoustic, Non-Acoustic Console
Jinwoo Bae Skills
Jinwoo Bae Education Details
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Kyungsung UniversityElectronics Engineering
Frequently Asked Questions about Jinwoo Bae
What company does Jinwoo Bae work for?
Jinwoo Bae works for Supernal
What is Jinwoo Bae's role at the current company?
Jinwoo Bae's current role is Sr. Actuation Engineer - Motor Controller at Supernal.
What is Jinwoo Bae's email address?
Jinwoo Bae's email address is ji****@****fran.fr
What schools did Jinwoo Bae attend?
Jinwoo Bae attended Kyungsung University.
What skills is Jinwoo Bae known for?
Jinwoo Bae has skills like Verilog, Xilinx Ise, Chipscope Pro, Embedded C, Code Composer Studio, Zigbee, Signal Processing, Sonar, Beamforming, Analysis, Fpga, C.
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