Jitendra Manjunath Gowda Email & Phone Number

Bengaluru, Karnataka, India

Executed the ASIC design flow for the 'ORCA_TOP' project in a 28nm technology, incorporating 9 metal layers, 40 macros,52k standard cells, and 4 clocks. This encompassed block-level floor planning, physical cell insertion, power planning,placement, timing closure, clock tree synthesis, and routing.•Exhibited expertise in developing optimized floorplans to meet high-performance targets, effectively addressing timingrequirements and resolving congestion issues through strategic grouping and weightage optimization.•Implemented critical path analysis, timing optimization, I/O constraint fixes, DRC fixing and post-route issue resolution usingEngineering Change Order (ECO).•Optimized Clock Tree Synthesis (CTS) and clock skew for enhanced performance.

Bengaluru, Karnataka, India

Complete knowledge of physical design like Floorplan, placement, Clock tree synthesis, routing, and also error fixing. Tools used synopsys ICC2, PrimeTime, StarRC,

Bengaluru, Karnataka, India

• Efficiently managed and maintained servers through remote access, ensuring uninterrupted operation and optimal performance.• Collaborated with clients to gather and understand their requirements, effectively translating them into actionable tasks for seamless implementation.• Employed robust security measures, including setting up firewalls and authorizing systems, to safeguard infrastructure and protect sensitive data within the HRA portal.

Master Of Engineering - Meng, Electrical And Microsystems Engineering

Bachelor Of Engineering - Be, Electrical And Electronics Engineering, 7.45/10

Activities and Societies: Participated in National level techno exhibition held at Ambedkar Institute of Technology Presented a paper.

Higher Secondary, Electronics, 84.5

Activities and Societies: CommunicationCompleted Higher Education in Electronics branch Got the knowledge of basic digital and analog.