To continue to improve on my technical abilities in the area of Electrical Engineering, FPGA Design, FPGA Verification, PCB Design, Programming, Artificial Intelligence and Machine Learning.
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OwnerDigital Art Works Apr 2020 - PresentOversee all business activities for business startup. Create preliminary design and prototypes of Art products using fiber optics and fiberglass. Design website using python Django and Adobe Animate for website animation. -
Business Owner - Emergent Engineering - Independent ContractorEmergent Engineering Feb 2018 - PresentWorked on multiple contracts with several companies such as Southwest Research, Concurrent Design Engineering, L3 Technologies, and National Instruments.
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Hardware In The Loop Test EngineerFirefly Aerospace Jun 2017 - Feb 2018Cedar Park, Texas, Us -
Avionics EngineerFirefly Space Systems Nov 2015 - Dec 2016Design of Lithium Ion battery pack for launch vehiclesDesign Battery Management System with the use of battery monitor IC’s, active/passive balancing, DC-DC convertersCreate PCB schematic/layout in Altium for Li-ion battery pack battery management system Create testbed for breadboard and brass board testing of battery management system Create requirement, procurement, test plan documentsDesign professional OEM product brochures using Adobe PhotoshopTest and evaluate Li-Ion 18650 cells
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Electronics Engineer IiNorthrop Grumman Electronic Systems Jun 2011 - 2015Falls Church, Va, UsFPGA Designer on multiple programsResponsible for FPGA design using Altera CPLD and Xilinx Virtex VWrote VHDL firmware for both designsIntegrated Common bus, HDLC, SPI, Ethernet, RS-232, MGT, and I2C protocols in designIntegrated Embedded Microblaze Processor Assisted test engineers in testing FPGA designFPGA designer using xilinx virtex 7 family. Tools used synplicity pro for synthesis and Vivado design suite implementation. Real Intent for RTL checking. Questasim for simulations. Implemented PCIe Gen 2. Simulink System Generator for DSP application. Interfaced with 10G fiber high SERDES. Designed ADC front end utilizing JESD204B high speed serial links at 6.4Gbs.Worked on a partial reconfiguration project on a VIrtex 7 device. Was able to dynamically change certain functions within the FPGA without reconfiguring whole device, loaded partial bin streams via JTAG, PCIe, or software. -
Systems Engineer InternBae Systems May 2011 - Aug 2011London, GbRF Target Development LabWorking under the supervision of a more experienced engineer, was responsible for setting up a test bed for Denial of service of 802.11 networks. Tasks included:Researching for compatible software/hardware for testing requirementsCreate Matlab GUI for test automationPerform testing of DOS techniques for 802.11 networksDocument and report final results to compare results from previous testingAccomplishments include gaining familiarity with setting up a proper test bed and learning about Azimuth channel emulator. -
Hardware Engineer InternNorthrop Grumman May 2010 - Dec 2010Falls Church, Va, UsWorking under the supervision of a more experienced engineer, was responsible for building and testing a simulator chassis to exercise interfaces to a space vehicle. Test set simulated MIL-STD-1553 and SpaceWire interfaces, and enabled early integration with the vehicle equipment. Tasks included:Creating assembly and test documentation, including detailed schematic, cable drawings, and interface panelWorking with technician to assemble chassisPerforming testing of chassis, including writing test procedure plan (50 pages)Interface with engineers to troubleshoot problems that occurredWriting complete user's guide (48 pages) for delivery to customerAccomplishments included gaining familiarity with seeing a job through from beginning to end including every last detail of the construction of the unit and its cabling. Also developed experience with VxWorks, Tcl (Tool Command Language), Visio, MIL-STD-1533, and SpaceWire.Responsible for FPGA design of Xilinx - Virtex 5 for DSP to output LVDS signals into an LVDS buffer interface. Tasks included:Writing VHDL code to implement 18 bit wide LVDS outputCreating memory core for FPGA to read data Verifing input/output waveforms of VHDL code in ModelSimCreating bit programming fileTesting output waveforms on Logic analyzerDeveloped experience with VHDL programming using ModelSim, Xilinx ISE, and Xilinx Core Generator -
Software Engineer/Hardware Engineer InternNorthrop Grumman May 2009 - Aug 2009Falls Church, Va, UsResponsible for troubleshooting preprocessor boards. Troubleshooting included debugging techniques using Max Plus II, Quartus II, and Corelis. Tasks included:Debugging computer software errors in C++ using Visual Studio and WorkbenchDebugging JTAG chain using traditional debugging techniquesAssisting experienced engineer in coming up with Boundary Scan Test to make for easier troubleshootingAccomplishments included gaining familiarity with JTAG chain of Altera devices. Developed experience using Quartus II, Max Plus II, and Corelis. AffiliationsSoftware consultant for IEEE organization. Responsible for creating workshops to provide entering engineering students exposure to the basic knowledge of software used by any engineer such as Matlab
Jj Garza Education Details
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Johns Hopkins Engineering For ProfessionalsAeronautical And Astronautical Engineering -
The University Of Texas At AustinArtificial Intelligence And Machine Learning -
The Johns Hopkins UniversityComputer/Electrical Engineering -
The University Of Texas-Pan AmericanElectrical And Electronics Engineering
Frequently Asked Questions about Jj Garza
What company does Jj Garza work for?
Jj Garza works for Digital Art Works
What is Jj Garza's role at the current company?
Jj Garza's current role is Owner at Digital Art Works.
What schools did Jj Garza attend?
Jj Garza attended Johns Hopkins Engineering For Professionals, The University Of Texas At Austin, The Johns Hopkins University, The University Of Texas-Pan American.
Who are Jj Garza's colleagues?
Jj Garza's colleagues are Praveen Pravu, Dwight Walker, Manuel Cadag.
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