Joe Mcgill Email & Phone Number

Austin, Texas Area

Currently serving as POWER9 chip post-silicon bringup lead, driving preparations for chip post-silicon bringup efforts. Conduct reviews of error isolation, debug, and reliability/serviceability features. Oversee test/execution planning activities for processor core/nest (uncore) areas. Develop and validate chip initialization, debug, and data extraction routines using in-house pre-silicon emulation environment (AWAN).

Austin, Texas Area

Owned development, maintenance, and debug of significant portion of POWER8 firmware code related to chip/system initialization and runtime servicability. Contributed to release of POWER8 firmware to open source community as part of OpenPOWER initiative.Supported functional verification of POWER8 chip and system offerings, spanning worldwide design, manufacturing and test groups.Presented IBM lab debug tools/techniques to OpenPOWER partner companies during workshop sessions in IBM Austin labs.Represented POWER Systems at IBM Insight/Interconnect conferences; interacted with IBMers, customers, and business partners in Solution EXPO booths covering POWER8 system offerings and chip capabilities.Interviewed professional/new-hire candidates for POWER verification organization.

Houston / Austin, Texas Area

Led POWER8 nest pre-silicon virtual bringup (VBU) activities. Validated pre-silicon function of POWER8 end-to-end system boot/initial program load (IPL) sequence, leveraging AWAN accelerator platform. Designed and implemented C++/assembly procedures forming backbone of IPL code, working in close cooperation with worldwide IBM firmware development teams.

Austin, Texas Area

Served as lead development engineer covering field support for POWER7 processor nest. Responsibilities ranged from isolation of module defects to client-facing resolution of SW performance issues. Participation in customer engagements led to direct realization of ~$20m in HW/SW sales revenue.Led bringup team of ~5 engineers performing POWER7 nest post-silicon validation efforts. Drove root-cause resolution of logic and performance issues. Developed and executed bringup testplan for fabric/SMP interconnect logic. Communicated status updates for worldwide bringup support teams. Execution of team/program validation goals resulted in successful ship of first-pass HW to early customers, one year ahead of historical IBM schedules.

Austin, Texas Area

Designed significant portion of POWER7 fabric/SMP interconnect logic, including implementation of asynchronous boundary communication logic used extensively throughout chip design. Responsible for VHDL design entry, block level stimulus/simulation, timing closure, resolution of simulation issues, and coverage analysis/takedown.Contributed to fabric portion of cycle-accurate C++ chip execution model for validation of high-level nest power/performance goals.

Austin, Texas Area

Directed field service actions and performed root-cause failure isolation for ~100 POWER5/5+ customer service events. Worked closely with physical failure analysis and processor development circuit teams to perform transistor-level isolation of circuit faults. Coordinated with design, product engineering, and firmware development teams to deliver high-quality firmware service pack updates to field.Owned POWER5+ LBIST code development and characterization processes used to gather data for circuit critical path analysis and performance tuning.Characterized POWER5 on-chip thermal monitoring subsystem, including calibration of thermal oscillator circuitry and performance analysis of core/nest throttling response mechanisms.Designed and executed testplan for post-silicon validation of POWER5/5+ FXU.

Austin, Texas Area

Developed POWER5+ load-store unit (LSU) support for little-endian execution mode.Added symmetric multithreading (SMT), dynamic power savings control logic, and population count execution engine to POWER5 fixed-point unit (FXU) design.Managed build and release of POWER5 processor core design data deliverables. Coordinated with design and management teams to structure VHDL releases and deliver chip-level simulation models.

Austin, Texas Area

Supervised laboratory sections for Introduction to Electrical and Computer Engineering and Digital Systems Engineering II. Assisted students with hands-on lab experiments and problem sets. Maintained course web pages, handouts, and student grades.

Greater St. Louis Area

Assisted dormitory residents with installation and maintenance of Ethernet connections to campus network/internet. Maintained dormitory computer clusters.

Greater St. Louis Area

Conducted help sessions and graded for undergraduate Algorithms and Data Structures course. Assisted students with homework sets and C++/Java programming assignments.

M.S., Electrical Engineering

Activities and Societies: IEEE, Phi Kappa PhiMicroelectronics and Computer Development (MCD) Fellowship Relevant Coursework: High-Speed.

B.S., Computer Engineering, Minor Business, Summa Cum Laude

Activities and Societies: Eta Kappu NuCalvin M. Woodward Engineering Fellowship Relevant Coursework: Digital Systems Engineering, Digital.