Jose Luis Cazarez Email & Phone Number

Guadalajara, Jal., Mx

Guadalajara, Mexico Metropolitan Area

Guadalajara, Mexico Metropolitan Area

Responsible of the technical activities of development, design and testing for 4x4 control modulesI represent the engineering team within project stakeholders including customer and core team

Guadalajara Area, Mexico

Still having fun, now at Vitesco Technologies!Transmission Control Units development.Owner of Electrical Engineering discipline Product Life-Cycle Documentation. Delivered on time and ready for each development gate.Owner of development of DFMEA For 4x4 Transfer Case Control Module and Transmission Control Units design. Delivered and updated after each design changeSupport for test bench board for transfer case control module, released the schematics to allow the construction of the load box.Transfer Case Control Module design support: Owner of selection of components based on calculation of power dissipation and performance. Owner of Analysis of thermal simulation based on power dissipation for complete design.

Guadalajara Area, Mexico

Still having fun!Transmission Control Units development.Owner of Electrical Engineering discipline Product Life-Cycle Documentation. Delivered on time and ready for each development gate.Owner of development of DFMEA For 4x4 Transfer Case Control Module and Transmission Control Units design. Delivered and updated after each design changeSupport for test bench board for transfer case control module, released the schematics to allow the construction of the load box.Transfer Case Control Module design support: Owner of selection of components based on calculation of power dissipation and performance. Owner of Analysis of thermal simulation based on power dissipation for complete design.

Guadalajara Area, Mexico

Transmission Control Units development.Owner of Electrical Engineering discipline Product Life-Cycle Documentation. Delivered on time and ready for each development gate.Owner of development of DFMEA For 4x4 Transfer Case Control Module design. Delivered and updated after each design changeSupport for test bench board for transfer case control module, released the schematics to allow the construction of the load box.Transfer Case Control Module design support: Owner of selection of components based on calculation of power dissipation and performance. Owner of Analysis of thermal simulation based on power dissipation for complete design.

Guadalajara Area, Mexico

Having fun, and...Functional SafetyFunctional Safety Certified Automotive Engineer; Functional Safety for lighting products, including Rear combination lamps, headlamps, single lamps and interior lamps Hardware Engineer Development of rear combination lamps from customer requirements, creating the architecture.Worst-case circuit analysis (WCCA) to support the proper selection of the components regarding the lamp functions and LED voltage/color/luminous flux groups.

Guadalajara Area, Mexico

Xilinx SOC FPGA Hardware and software development

Guadalajara Area, Mexico

- Responsible of regressions for multiple projects, giving coverage and test results. Figures presented in project forums and interacting with managers, architects, designers and validators. Issues directed to the correct owner and helped to found solutions on project forums.- Implemented design for testability logic for server products using Verilog and perl. Logic was generated using perl scripts to automate the process for many structures inside server product, increasing the speed and reliability of the final code in Verilog.- Verificated design for testability logic for server products using Verilog, Perl and Specman. A number of bugs were found using automation to generate test cases, implementation of test environment using specman helped to find bugs.- Validated Logic (transistor logic verification) for server products, bugs on layout and RTL implementation were found on this stage and escaped from previous steps of validation.- Owned of Gate level verification for communication (T1, E1) and high-speed interface observability ASICs. Implemented using the test environment from RTL and including timing information. Many bugs were found from layout and RTL implementations.- Developed RTL and verification for T1/E1/J1 communications VOP framer using VHDL. First Intel GDC chip created and validated in Guadalajara.- Owned analog validation for memory interfaces (DDR1, DDR2, FBD) in servers. Interaction with memory suppliers, sellers, interface designers, architects, platform designers, technicians. Bugs found on different levels of design: platform design, memory implementation, test probe implementations, BIOS.

Tlaquepaque Area, Mexico

Owned the definition and execution of DDR1 and DDR2 signal marginality validation for different platforms, automated the execution of the memory tests, saving more than 80% of the time, so we could execute many test scenarios with different temperatures, voltages and moving electrical parameters with high confidentiality.Coordinated the purchasing of early DDR1 and DDR2 DIMMs, as I was testing new memory controller for that technology. Lead a small team of technicians in lab for memory testing, including definition of new required reworks and mentoring them about the company culture and job requirements.Found critical issues on DIMMs and interface configuration from BIOS.

Tlaquepaque Area, Mexico

- Owned the hardware development for eight submodules for an E1-T1 framer; developed arbiter for reads/writes to internal buses, T1/E1 and E1/T1 mapper, synchronizers for data between different clock domains.- Owned gate level test for the E1-T1 framer, implementing for the first time this methodology on Guadalajara design center. - An important amount of new bugs were found under this level of testing, most of them related with timing violations and metastability. Those kind of problems could not be detected in previous stages of the framer development and testing. - A test cases collection was selected from functional RTL level to cover the framer functionality in gate level and new test cases developed in order to test significant functionality of addressing space in a short period of simulation time. - Asynchronous modules as back plane and pli was tested in order to detect problems with timing violations and metastability problems, also all the timing violations generated by our tests was analized in order to detect timing problems in synchronous flip flops. - Timing back annotation was used for the first time, this feature helped also to have a more realistic simulation and new bugs related with timing were found.- Owned Regressions for T1-E1 product in pre-silicon. The automation of the process allowed the total execution and analysis for the final release to be completed in two weeks, saving execution time and resources.- SONET ASIC functional verification for registers using scripting to accelerate the process. The scripting helped the verification team to quickly update register information from older to new releases.

Guadalajara Area, Mexico

- Owned the implementation in VHDL for communications chip used on voice over IP protocols; - Developed RTL code and test cases for T1/E1/J1 framer; owned synchronizers and T1-E1 and E1-T1 mapper implementations.

Tabasco, Mexico

- Development of Power control test laboratory, saving money and effort by testing the power control units on lab, reproducing oilfield conditions that helped us to solve problems and fix issues.- Electric/electronic material recovery. Recovered complete control units and industrial switches, motors, saving important amount of money and having backup material for emergencies on oilfield electrical failures.- Power control room maintenance. Reconstructed complete power control rooms for re-use on oilfields. It allowed the company to have the drilling equipment ready for the electrical requirements on time.

Villahermosa Area, Mexico

- On site maintenance of instrumentation panels for industrial engines - Reconstructed instrumentation panels for diesel - electric generators during drilling operation at oilfields, saving time and protecting the diesel engines from crashing on overloading.- Test of electronic gauges for pressure, temperature, and speed.

Advanced Program Of Semiconductors Technology Design (Padts), Asics Digital Design

Mse

Ingenieria Electronica