Jonathan Lopez-Morell Email & Phone Number
@intel.com
2 phones found area 408
LinkedIn matched
Who is Jonathan Lopez-Morell? Overview
A concise factual answer block for searchers comparing this professional profile.
Jonathan Lopez-Morell is listed as Design Engineering Manager; Hiring Manager at Intel Corporation, a with 10 employees, based in Elk Grove, California, United States. AeroLeads shows a work email signal at intel.com, phone signal with area code 408, and a matched LinkedIn profile for Jonathan Lopez-Morell.
Jonathan Lopez-Morell previously worked as Design Engineering Manager & Hiring Manager at Intel Corporation and Senior Component Engineer at Intel Corporation. Jonathan Lopez-Morell holds Phd, Electrical Engineering from Michigan State University.
Email format at Intel Corporation
This section adds company-level context without repeating Jonathan Lopez-Morell's masked contact details.
AeroLeads found 1 current-domain work email signal for Jonathan Lopez-Morell. Compare company email patterns before reaching out.
About Jonathan Lopez-Morell
Engineering Manager with many years as Senior Component Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Career Development, Management, Microprocessors Design Cycle, High-Speed Circuit Design, Application-Specific Integrated Circuits (ASIC), TCL, Synthesis and APR Flows. Strong engineering professional with a PhD focused in Electrical Engineering from Michigan State University.
Listed skills include Low Power Design, Static Timing Analysis, Semiconductors, Timing Closure, and 10 others.
Jonathan Lopez-Morell's current company
Company context helps verify the profile and gives searchers a useful next step.
Jonathan Lopez-Morell work experience
A career timeline built from the work history available for this profile.
Design Engineering Manager & Hiring Manager
Senior Component Engineer
In this position I am responsible for the design and development of various high-speed circuits for core and uncore microprocessor products. It covers reviews of product requirements and architectural descriptions, RTL-Verilog development and validation, manual schematic entry and synthesis, performance/quality validation and power optimization. In this role I am also responsible for device level validation, characterization, and chip level layout.In this position I have help defining methodology of Synthesis, Placement, Routing, Static Timing analysis, Timing closure, Low power implementation with the state of the art industry standard Synopsys tools like Design Compiler Topographical, ICC, Power Compiler and others from Cadence like Conformal.
Bible Teacher
Bible teacher with years of expierence teaching biblical studies. Main teaching interests/areas: Christian Educaction, Pedagogy, Hermeneutics and Christian Couseling.Experience with planning and organization of Bible classes, curriculum selection and teaching resources.
Graduate Student
Colleagues at Intel Corporation
Other employees you can reach at intel.com. View company contacts for 10 employees →
Seema Bhat
Colleague at Intel CorporationBayan Lepas, Penang, Malaysia
View →
AK
Ajeesh K Shanmughan
Colleague at Intel CorporationThrissur, Kerala, India
View →
EM
Edgar Mmadi
Colleague at Intel CorporationCity Of Johannesburg, Gauteng, South Africa
View →
SE
Steven Edwards
Colleague at Intel CorporationChandler, Arizona, United States
View →
HV
Hector Vivanco
Colleague at Intel CorporationUnited States
View →
MS
Mitsu Shah
Colleague at Intel CorporationMumbai, Maharashtra, India
View →
AP
Alma Patricia Perez
Colleague at Intel CorporationPortland, Oregon Metropolitan Area, United States
View →
VV
Vicky Venditto
Colleague at Intel CorporationAlbuquerque, New Mexico, United States
View →
DS
Dennis Sanders
Colleague at Intel CorporationAlbuquerque, New Mexico, United States
View →
TG
Thomas Grover
Colleague at Intel CorporationCasa Grande, Arizona, United States
View →
Jonathan Lopez-Morell education
Phd, Electrical Engineering
Ms, Electrical Engineering
Bs, Electrical Engineering
Frequently asked questions about Jonathan Lopez-Morell
Quick answers generated from the profile data available on this page.
What company does Jonathan Lopez-Morell work for?
Jonathan Lopez-Morell works for Intel Corporation.
What is Jonathan Lopez-Morell's role at Intel Corporation?
Jonathan Lopez-Morell is listed as Design Engineering Manager; Hiring Manager at Intel Corporation.
What is Jonathan Lopez-Morell's email address?
AeroLeads has found 1 work email signal at @intel.com for Jonathan Lopez-Morell at Intel Corporation.
What is Jonathan Lopez-Morell's phone number?
AeroLeads has found 2 phone signal(s) with area code 408 for Jonathan Lopez-Morell at Intel Corporation.
Where is Jonathan Lopez-Morell based?
Jonathan Lopez-Morell is based in Elk Grove, California, United States while working with Intel Corporation.
What companies has Jonathan Lopez-Morell worked for?
Jonathan Lopez-Morell has worked for Intel Corporation, Iglesia De Dios Sacramento, and Michigan State University.
Who are Jonathan Lopez-Morell's colleagues at Intel Corporation?
Jonathan Lopez-Morell's colleagues at Intel Corporation include Seema Bhat, Ajeesh K Shanmughan, Edgar Mmadi, Steven Edwards, and Hector Vivanco.
How can I contact Jonathan Lopez-Morell?
You can use AeroLeads to view verified contact signals for Jonathan Lopez-Morell at Intel Corporation, including work email, phone, and LinkedIn data when available.
What schools did Jonathan Lopez-Morell attend?
Jonathan Lopez-Morell holds Phd, Electrical Engineering from Michigan State University.
What skills is Jonathan Lopez-Morell known for?
Jonathan Lopez-Morell is listed with skills including Low Power Design, Static Timing Analysis, Semiconductors, Timing Closure, Microprocessors, Logic Synthesis, Vlsi, and Cadence.
Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.
Start free trial