Joshua M. Email & Phone Number

Tucson, Arizona Area

• Working on projects in a number of areas including resource management/program compilation for heterogeneous SoCs & design of novel architectures for neuromorphic computing
• Regularly work with a number of languages/frameworks including C, C++, Python, Verilog, LLVM IR, & CUDA
• Experience with FSBL + U-Boot + Linux development through Yocto-based construction and customization of a software stack for an ARM-based heterogeneous research SoC
• Developing a large skillset for RTL design + debug along with rapid IP synthesis and integration via modern HLS toolchains

Phoenix, Arizona Area

• Java/Javascript development on large open source projects maintained by the Codice Foundation as well as private projects downstream of those
• My areas of work included:- Java based XML parsing and data remediation/processing built around the OSGi Framework- REST endpoint development with a Paxweb + Jetty + JAX-RS/SparkJava stack- Performance testing/analysis.

• Worked on Verilog implementation of an FPGA channelizer module
• Implemented a heavily parameterized FFT architecture with support for arbitrarily sized FFTs and adjustable runtime
• Designed and implemented peripheral components including resource optimal filters and memory layout+controller logic to enable continuous, streaming operation.
• Built a supporting set of MATLAB scripts to prepare data for and process data from Vivado simulations for use in functional verification of components.
• Analyzed tradeoffs between various Xilinx FPGA offerings and made recommendations for specific architectures based on performance goals of the final design.

Tucson, Arizona

• FPGA development for an export controlled project called "High Speed Reconfigurable SIGINT (HiReS) System for Large Time-Bandwidth Product" that explored heterogeneous architectures for use in a high throughput signal.

• FPGA work with implementation and customization of Xilinx GTX and GTH Transceivers for optical communication across and between a variety of Virtex 7 platforms to meet application specific needs for planned ATLAS.
• Utilized a combination of VHDL and Verilog as the need arose
• Gained familiarity with Xilinx IP customization and the usage of Xilinx datasheets/user guides
• Developed a working knowledge of high-speed serial I/O and fiber communications

• Worked with various aspects of in-house live sports production including grip, graphics, replay, and some camera work. Worked at Football, Men's & Women's Basketball, Baseball, and Women's Soccer.
• Gained experience in areas like operating replay with Tightrope Zeplay, operating and creating graphics in Ross Xpression and ClickEffects Blaze, calibrating cameras with a CCU, and using various cameras including.

• Served as an undergraduate lab assistant for ECE 274A, Arizona's "Introduction to Digital Logic"​ class.
• During lab sessions, helped students work through designing, implementing, testing, and debugging their Verilog-based lab assignments, both through simulation and on the lab's Spartan 3E starter boards.

Rochester, Michigan

• Ten week REU (Research Experience for Undergraduates) program
• Under the mentorship of Dr. Daniel Llamocca, modeled the CORDIC algorithm in MATLAB, developed two scalable architectures for implementing CORDIC in VHDL -- a fixed-point and a floating-point implementation -- and used.
• Performed a full design space analysis of each of these architectures to determine what configurations give the best accuracy for the least FPGA resources, execution time, etc.
• Produced one poster and two papers, one of which was accepted to and posted in ReConFig 2015 proceedings and the other published as a technical report.