James Chang Email & Phone Number

Santa Clara, Ca, Us

San Jose, Ca, Us

Sunnyvale, California, Us

Collaborating with cross-functional teams the enablement of planar and deep submicron finFet processes (10nm):• With IP Teams:- Support Embedded Memory and Mixed-Signal IPs- PDK installations; foundry data management- SPICE-based simulator qualifications on all new processes- Evaluate, propose layout methodologies in aligning with latest finFet processes- New EDA tool enablement and adoption by the IP Design team• With EDA Tools Teams:- Recommend and drive any new features and enhancements on EDA Tools- Negotiate and set priorities on to-be-fix items- Collaborate and build a tool regression suite• With Program Managers:- Constant sync-up meetings with PMs in reviewing IP release schedules- Being informed about update specs from customers and new release schedules from foundries, etc.• With Information Technology Team:- Compute farm management- EDA Tool license management

Us

• Tasks performed at SpectraLinear:• Sole CAD person supporting local and global design centers.• Architect in designing and implementing the CAD flow for the company’s engineering group. Major responsibilities include setting up Cadence CAD platform; scripts automation (shell and SKILL); automating the design management system; Verilog modeling; layout rule implementation; automating place and route flow; tape out automation; foundry interfacing and wafer tracking.Result: Propelled a successful tape out for the first product 6 months after the company’s founding. The product is functional on first silicon• Design tasks performed at SpectraLinear:• Place and route on chip designs• Laying out of design blocks, run and debug DRC/LVS runs• Implemented multiple CD flows in SKILL, Tcl, Perl and shell scripts• Corporate computer and IT network management – set up and maintain the corporate network infrastructure, implemented backups, setup corporate virus protection and successfully set up 3 international remote design sites ensuring uninterrupted connection and transmission of design updates.Result: Productivity significantly increased

Palo Alto, Ca, Us

• Managed a methodology team of 10 in supporting various internally developed design tools for the Microprocessor Design Group. Major responsibilities include leading the methodology team in interfacing with customers on design tools and flows issues; specifying tool methodologies, establishing and reviewing next tool release cycle features with the development teams; testing, correlating new features and deployment of new tools. Supported tools include: Static Timing Analyzer, Transistor Level Timing Tool, Noise Analyzer, Electrical Rule Checker, Characterization and Power Estimation.Result: Resulted a successful and timely tape out for the Niagara product and functional on first silicon

San Jose, Ca, Us

• (Acquired by Cypress, formerly International Microcircuits Inc.) Managed a CAD/library group in supporting the Clock and Timing design team of 50 engineers at local and remote design centers. Successfully integrated IMI’s CAD flow and network system with Cypress’ three months after the acquisition.Result: Led the company in profitability for the past 10 quarters (division annual revenue: $170M)• (Prior to the acquisition) Successfully started-up both CAD and layout groups in supporting the company’s Clock and Timing organization (annual revenue: $60M). Led, mentored and stabilized the engineering organization when the VP of engineering passed away unexpectedly. Led the team in re-engineered the Mixed Signal design flow, upgraded hardware and software environment. Characterized the library for Mixed Signal devices, support Verilog models for digital cells and PLLs, jitter simulation for PLLs, layout verification for Mixed Signal and Clock devices, IBIS modeling for all IOs and chip design tape out signoff.Result: Minimized interruption on the tight design-cycle-time; eliminated costly layout and tape out errors

San Jose, Ca, Us

• Managed a CAD group in supporting the design group and the layout group for the ASIC product organization• Implemented the library management system for all the standard cell libraries.Result: all cells are revision controlled and all cell views are synchronized• Enhanced the post-layout verification program to greatly improve the post chip layout turn-around-time by 100%• Enhanced the cell verification tool so as to improve cell library integrity

Santa Clara, Ca, Us

• Developing mixed-signal library cells for the network design group• Implemented one of the industry’s first automated library characterization systemPublication Speaker: Automating Circuit Simulation and Evaluation for the Semi-custom IC Design Process, ASIC Conference and Exhibit, Rochester 1992

Us

Design ECL, TTL circuits; performed failure analyses, parasitic extraction via manual calculation

Msee, Semiconductor Physics

Bsee/Math, Ee & Cs

Secondary School Diploma