Joe Doucette Email and Phone Number

Xeon Power Management Firmware Team:Responsible for reset and power management features for Xeon server and workstation products. Subject matter expert for firmware patching. Ran team sustaining engineering lab supporting legacy products. Engaged in code and production patch reviews focusing on security vulnerabilities.Granite Rapids, Sierra Forest:Pcode design execution lead for Xeon 6 family. Migrated from custom microcontroller to Tensilica microcontroller, implementing a new modular design in C++. Supported both big and little core SOC projects from a single repository.Coordinated closely with external teams for milestone alignment.Collaborated with team's DevOps & automation teams to migrate from legacy flows to GitHub & Jenkins, introducing efficiency improvements, introducing nightly Si regression of firmware images, reducing bug escapes.Arctic Sound, Ponte Vecchio, Icelake Server, Sapphire Rapids:Lead for server graphics Pcode development, debug, and patching. Defined key Pcode features in collaboration with PM and VPG arch. Worked to define patching and firmware load flows, ensuring validation with RTL simulation/emulation teams. Led simplification efforts in DRAM power management, enhancing system performance and reliability. Influenced the redesign of DRAM RAPL features.Haswell Server (Xeon E5/E7 v3 series):Firmware team project lead, responsible for reset sequence, overclocking features, and power management. Developed DRAM thermal management systems and running average power limit mechanisms. Aligned team schedules and collaborated with project teams for bug triage and mitigation.Sandy Bridge EP (Xeon E5 series):Led implementation of socket and DRAM Running Average Power Limit features. Provided post-silicon debug support, managed patch changes, and collaborated with validation for effective bug mitigation.Nehalem-EX (Xeon 7500 series):Owned package power management features. Supported post-si with feature additions & workarounds.

Developed real-time embedded software for Digital Receiver/Exciter modules for Early Warning Radars in a CMMI Level 4 environment. Ported BSP from VxWorks 5.5 to 6.1 and enhanced to support platform HW. Performed benchmarking on key algorithms and OS functionality on platform HW. Implemented and supported SW build/debug environment. Developed and integrated platform initialization, Ethernet/command processing, CPU diagnostics, event log, and common environment variable support. Developed debug tools to test network protocol compliance, collect/process/analyze received data, and emulate Data Processor/Signal Processor interfaces.Worked with HW engineers to bring up, debug, and characterize module functionality. Worked with FPGA engineers to debug CPU to FPGA interfaces, including peripheral and PCI-X bus interfaces. Worked with FPGA engineers to diagnose & correct FPGA logic problems.

Worked for HPTC Visualization group doing FPGA design for a video compositing card. Developed FPGA functionality for PCI-X logic core integration. Developed module diagnostics including tests for DDR memory and synchronization connector.Worked for AlphaServer Firmware group developing server management firmware for AlphaServer GS1280 series of computers. Responsibilities included developing functionality for self test, hardware abstraction, control panel interface, failsafe loader, synchronization of state across micros. Also implemented and supported build/development environments, Manufacturing and Field Service inquiries relating to test and analysis of failed hardware, and maintained network protocol documentation.Summer intern for AlphaServer Firmware group enhancing and designing nightly regression scripts for AlphaServer platforms.

Worked summers 1996-1999 including a co-op from May 1998-December 1998Designed Windows NT security manager component and Visual Basic 6.0 ActiveX components to control robotic systems and interface to third party equipmentMaintained and enhanced automated test hardware and software. Maintained and enhanced robot firmware.