Joe Kidd Email & Phone Number

Boston, Ma, Us

Santa Clara, California, Us

Santa Clara, Ca, Us

● Manage team through transformation from large functional org to IP/SOC model, changing ownership, accountability, and cross-functional working model to enable scaling to multiple parallel programs● Developed strategy and funding plan to diversify engineering staffing to worldwide sites● Presented executive management with engineering budgets for $100M+ development programs● Driver of cultural change from startup mentality to enterprise-focused development; created a track record of predictable execution and executive visibility into programs● Developed headcount and execution plans for my ~100 person SOC team and ~200 matrixed engineers spread across 8 sites in 3 countries● Own execution of lead-development project in each generation; support multiple other project teams in building highly efficient derivatives● Create physical design, RTL integration, and portable verification methodology for each project generation● Manage cross-functional SOC team, including RTL, verification, firmware, physical design, DFT, technical writing, program management, analog integration, emulation

Sunnyvale, California, Us

● Engineering product line owner for DDR PHY designs, creating alignment between marketing requirements, customer feature requests, and R&D bandwidth of my team of 200+ engineers located across 6 countries● Memory interface director charged with overhauling the downstream user experience for memory interface products, including SOC integration, software development, support escalations; always asking “How can we make things better?”● Displaced internal and external competition with industry-leading memory interface design, beating PPA targets and streamlining customer integration● Managed 2nd-level support escalation team, resolving critical issues for high-volume customers worldwide● Provide mentoring in leadership development, growing effective leads and managers; produced future directors and principal engineers out of my org at double the rate of adjacent teams● Led a team to create cross-functional solutions to redefine workflows in response to changed needs

Santa Clara, California, Us

● Drive execution of DRAM interface IP across 6 process technologies and 5 DRAM protocols● Key contact representing AMD’s entire mixed-signal IP portfolio to game console customer● Cross-functional technical lead of 65-person team building DRAM interface---> Principal timing performance architect, developing analysis code for design---> Coordinate with architects to develop feature roadmap---> Manage cross-team interactions across RTL, verification, and physical designers---> Develop reuse approach to leverage components in support of multiple products● Granted multiple patents in modeling and verifying clock-domain-crossing hardware● Member of architecture team, focused on feasibility, power efficiency, and portability

Wilmington, Ma, Us

● Responsible for full-custom digital design, verification, and silicon debug● Senior circuit designer for audio codec chips sold into high-volume markets● Drove microarchitecture and circuit design of TLB and L1 cache for low-power DSP core