Manage IP Support Team• Responsible for integration of High Speed SerDes and other IPs into multiple Customer ASICs• Work simultaneously with Multiple projects on:o IP selectiono Floor planning guidanceo Clocking advise and guidelineso Integration of Verilog modelso Startup simulations, Synthesis guidelines, STA and DFT guidelines and supporto Documentation for Integration o Design and documentation of multiple RTL wrappers to aid in integration of SERDES into ASIC PIPE wrapper DFT wrappers DFE Controllers• Planning and Scheduling for IP packaging activities for multiple projects across multiple technologies from 90nm to 28nm FDSOI• First line interface with multiple customer ASICs o Work with project timelines and requirements so that IP deliveries and support could be managed in time-critical projects• Managed Verification teamo Verification of SerDes digital circuitry • Specified ARM hardening activities for several projects• Initial digital design of first S3 130nm SerDes• Support of all subsequent generations from 130nm, 65nm, 32nm to 28nm FDSOI

• Led team of 3 physical designers on ASIC implementation in 65nm• Developed unique solution for timing sign-off in mixed voltage architecture• Provided design and flow support for customer• Worked with internal ST team to port ARM core to meet requirements• Managed and supported all IP deliveries (SerDes, ARM core, PLLs, Custom IOs)• Project Lead for several Customer ASICs• Completed in parallel with on-going IP management tasks and responsibilities

• Led team that developed a working Gigabit Ethernet PHY and maintained a Fast Ethernet product portfolio• Managed System Analysis, Digital design, Verification and Lab validation teamso Teams in multiple sites and countries• Ensured analysis and specifications were created for Analog Design team• Ensured all system, design, verification and validation documentation was completed and maintained• ASIC prime and digital design lead. RTL design, synthesis and DFT tasks• Ensured full University of New Hampshire compliance was achieved• Several Customer visits to promote Fast Ethernet and Gigabit Ethernet products• Completed 2nd generation Gigabit Ethernet PHY as embeddable IP in 90nm

• Worked in Joint development project with Nortel Networks on G.Lite ADSL chip set• Chip prime for CPE implementation of G.Lite chip seto Design teams in Italy, France and Ottawao Specified design activities for multi-site ST teams• Interfaced with design partners from initial project start-up to silicon success• Multiple Customer visits to win business

• Managed Hardware, ASIC, RF design, PCB design and Lab validation groups of GPS design company• Multiple OEM board versions produced for high performance surveying and tracking applications

• Successfully completed three generations of GPS/GLONASS correlator ASIC• Developed innovative solutions that allowed tracking of encrypted GPS signals• Developed innovative solutions that allowed simultaneous tracking of both GPS and GLONASS satellites• Responsible for all RTL design, synthesis, DFT insertion, verification and documentation• Always had first time silicon success that allowed multiple successful product line to be developed• Worked with software integrators to get optimal performance from ASICs

• Designed, built and tested RF frontend for GPS receivero Antenna, LNA, RF filters, mixers, IF filters, gain stages and A/D convertors• Designed, built and tested baseband digital decimation filter• Field trials of completed GPS receiver• Investigation into different technologies for in-city navigationo Designed and built transmitter/receiver that would be attached to lamppost to relay location and yellow pages information to passing cars