Chief System ArchitectResponsible for defining the System Architecture and Design of the next generation patient monitor products. • Defined the System Architecture for the next generation patient monitor product family • Designed Analog and Mixed Signal data acquisition hardware to measure patient parameters such as ECG, SpO2, IBP • Designed and verified several FPGAs • Designed Battery / Power Management subsystem • Modeled signal paths using MATLAB/Simulink

Principal System ArchitectResponsible for the system architecture and hardware of the Value Segment Solutions (VSS) group which was focused on developing products for the global emerging markets. • Set the technical direction and provided technical leadership for the VSS Research and Development teams located in Andover, Shanghai and Sao Paulo. • Analyzed customer needs for low cost high performance patient monitoring products. • Defined the System Architecture for several patient monitoring product lines targeted at the value segment. • Designed the hardware for the patient monitor product lines. • Actively involved in product development which included: • Detailed Analog, Digital and Mixed Signal hardware design • FPGA Design and Verification • Embedded System Design • Battery / Power Management Design • Drove compliance to relevant medical product regulatory standards. • Worked closely with the supply chain team to ensure DFM and efficient NPI for the new monitoring products.

Senior Technical Staff Technical lead for the team that designed the Memory Management Unit (MMU) of the Millennium SPARC Microprocessor. The development of the MMU used standard cell and custom logic design and synthesis flows. • Responsible for: • Definition of the MMU • Partitioning of the design into standard cell or custom flow • Performance verificationThe logic design was captured using Verilog HDL. The logic synthesis was done using the Synopsis tool set and simulation was done using the VCS simulator. The Cadence IC tool suite was used for custom cell design, as well as place and route optimization.