John Ayers Email & Phone Number

Highly accomplished and passionate Principal Engineer with over 28 years of experience in the semiconductor industry specializing in design, verification, and SoC and system architectures. My career is filled with direct involvement in RTL design, SOC assembly, microcontrollers, analog circuits, BIOS/UEFI, methodology, scripting, floorplan, on-die and system interconnect, specification authoring, and debug. Proven leadership in managing teams and building strong and vital cross-functional collaborations through complex projects. Patent and publication proven track record of innovation within semiconductor architecture. Experience with SOC on-die primary and secondary interconnect fabrics, as well as the past and latest generations of high-speed IO architecture and of interconnect standards (e.g. PCIe, CXL, UCIe. DDR, Ethernet, HBM, etc.). Experience with industry standards (e.g., PECI, UCIe, IEEE, JEDEC, AMBA). Knowledge of die/chiplet design, 3D/stacked packaging, and heterogeneous integration techniques. Understanding of advanced packaging technologies (e.g., TSVs, interposers). Experience in architecting and designing scale-out large-scale, high-performance (HPC) silicon systems. Knowledge in die/chiplet communication protocols, power management, and fabrication process defect & reliability challenges. Understanding of simulation/emulation/behavioral-modeling tools and hardware verification techniques. Strong communication and presentation skills. Problem-solving and analytical mindset. Looking for a multi-faceted role in SoC design, using my varied experience across the entire product life cycle.

Listed skills include Computer Architecture, Processors, Soc, Debugging, and 42 others.