- Digital design work across multiple tape-outs supporting the entire chip development cycle- Owner of MAS and RTL developments supporting USB4/3 functions including logical layer, transport layer, and sideband communications for hub devices- Collaborate with DV teams to develop block level verification test plans and UVM test environments. Resolve hardware bugs within various design elements and IP - Utilize Xilinx FPGA platforms to assist firmware and layout teams with testing of functional hardware modes using ChipScope to analyze failures- Perform certification testing on pre-production silicon. Debug hardware and firmware issues using Teledyne LeCroy logic analyzers to identify bugs that require ECO- Manage full chip Lint/CDC environments for 15 designers to ensure clean designs pre tape-out. Create and maintain Python scripts for error filtering, report generation, and waiver processing

- Supported the SurfScan metrology, review cluster, and wafer defect inspection system at Intel's fab

- Designed a hardware testing demo on a ZCU102 FPGA in C showcasing the latency, throughput, and bandwidth of RapidIO high speed serial communication. Wrote Linux device drivers to manage packet transactions across the interface- Assisted Engineers in developing data capture software by writing and testing Python scripts to organize incoming packet data into logs for use in data visualization tools. Wrote technical documentation allowing company engineers to understand the implementation of the scripts

- Interacted with Oregon State University members to provide computer, printer, and network support using interpersonal communication skills to provide technical solutions for customers